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公开(公告)号：US10211140B2
公开(公告)日：2019-02-19
申请号：US15616009
申请日：2017-06-07
IPC分类号： H01L23/498 , H01L23/367 , H01L21/52 , H01L21/48 , H01L23/538 , H01L23/00
摘要： A method for forming an electronic device includes embedding an integrated circuit die in a package including substrate of thermally conductive material with front and back surfaces and a through-hole. The die is sunk in the through-hole. A first insulating material layer covers the die front surface and the package front surface with first windows for accessing die terminals. Package terminals and package track are arranged on the first insulating layer. A second insulating material layer covers the first insulating layer and the package tracks with second windows for accessing the package terminals.
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公开(公告)号：US20170271254A1
公开(公告)日：2017-09-21
申请号：US15616009
申请日：2017-06-07
IPC分类号： H01L23/498 , H01L23/538 , H01L21/48 , H01L21/52 , H01L23/00 , H01L23/367
CPC分类号： H01L23/49838 , H01L21/4857 , H01L21/52 , H01L23/367 , H01L23/3677 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L2224/0401 , H01L2224/04105 , H01L2224/16227 , H01L2224/16235 , H01L2224/18 , H01L2224/32245 , H01L2224/73253 , H01L2224/73267 , H01L2224/92144 , H01L2224/92244 , H01L2924/15153 , H01L2924/16195 , H01L2924/18162
摘要： A method for forming an electronic device includes embedding an integrated circuit die in a package including substrate of thermally conductive material with front and back surfaces and a through-hole. The die is sunk in the through-hole. A first insulating material layer covers the die front surface and the package front surface with first windows for accessing die terminals. Package terminals and package track are arranged on the first insulating layer. A second insulating material layer covers the first insulating layer and the package tracks with second windows for accessing the package terminals.
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公开(公告)号：US20170250128A1
公开(公告)日：2017-08-31
申请号：US15282619
申请日：2016-09-30
IPC分类号： H01L23/495 , H01L49/02 , H01L21/56 , H01L23/31 , H01L21/48
CPC分类号： H01L23/49589 , H01L21/4825 , H01L21/565 , H01L23/3107 , H01L23/3114 , H01L23/49503 , H01L23/4952 , H01L23/49541 , H01L23/49548 , H01L23/49575 , H01L23/49582 , H01L23/49586 , H01L28/60 , H01L2224/16245 , H01L2924/181 , H01L2924/00012
摘要： In an embodiment, a method of integrating capacitors in semiconductor devices includes: providing a lead-frame for a semiconductor device, the lead-frame including one or more electrically conductive areas, forming a dielectric layer over the electrically conductive area or areas, forming an electrically conductive layer over the dielectric layer thus forming one or more capacitors including the dielectric layer sandwiched between an electrically conductive area and the electrically conductive layer, and arranging a semiconductor die onto the lead-frame by providing electrical contact between the semiconductor die and the electrically conductive layer.
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公开(公告)号：US09704794B2
公开(公告)日：2017-07-11
申请号：US14733209
申请日：2015-06-08
IPC分类号： H01L23/06 , H01L23/04 , H01L23/498 , H01L23/367 , H01L21/52 , H01L21/48 , H01L23/538
CPC分类号： H01L23/49838 , H01L21/4857 , H01L21/52 , H01L23/367 , H01L23/3677 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L2224/0401 , H01L2224/04105 , H01L2224/16227 , H01L2224/16235 , H01L2224/18 , H01L2224/32245 , H01L2224/73253 , H01L2224/73267 , H01L2224/92144 , H01L2224/92244 , H01L2924/15153 , H01L2924/16195 , H01L2924/18162
摘要： An electronic device includes a circuit integrated on a die having front and back surfaces with die terminals on the front surface. The die is embedded in a package including substrate of thermally conductive material with front and back surfaces and a through-hole. The die is sunk in the through-hole. A first insulating material layer covers the die front surface and the package front surface with first windows for accessing die terminals. Package terminals and package track are arranged on the first insulating layer. A second insulating material layer covers the first insulating layer and the package tracks with second windows for accessing the package terminals.
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公开(公告)号：US11521861B2
公开(公告)日：2022-12-06
申请号：US16994049
申请日：2020-08-14
发明人： Michele Derai , Giovanni Graziosi
IPC分类号： H01L21/48 , H01L21/56 , H01L21/78 , H01L23/31 , H01L23/495
摘要： Semiconductor dice are arranged on a substrate such as a leadframe. Each semiconductor die is provided with electrically-conductive protrusions (such as electroplated pillars or bumps) protruding from the semiconductor die opposite the substrate. Laser direct structuring material is molded onto the substrate to cover the semiconductor dice arranged thereon, with the molding operation leaving a distal end of the electrically-conductive protrusion to be optically detectable at the surface of the laser direct structuring material. Laser beam processing the laser direct structuring material is then performed with laser beam energy applied at positions of the surface of the laser direct structuring material which are located by using the electrically-conductive protrusions optically detectable at the surface of the laser direct structuring material as a spatial reference.
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公开(公告)号：US09428380B2
公开(公告)日：2016-08-30
申请号：US14686540
申请日：2015-04-14
CPC分类号： B81B7/0064 , B81B2201/0257 , H01L2224/48091 , H01L2224/48137 , H04R1/021 , H04R1/04 , H04R19/005 , H04R19/04 , H04R31/006 , H04R2201/003 , H04R2201/029 , H05K9/0009 , H01L2924/00014
摘要： One or more embodiments are directed to encapsulating structure comprising: a substrate having a first surface and housing at least one conductive pad, which extends facing the first surface and is configured for being electrically coupled to a conduction terminal at a reference voltage; a cover member, set at a distance from and facing the first surface of the substrate; and housing walls, which extend between the substrate and the cover member. The substrate, the cover member, and the housing walls define a cavity, which is internal to the encapsulating structure and houses the conductive pad. Moreover present inside the cavity is at least one electrically conductive structure, which extends between, and in electrical contact with, the cover member and the conductive pad for connecting the cover member electrically to the conduction terminal.
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公开(公告)号：US08854830B2
公开(公告)日：2014-10-07
申请号：US13779592
申请日：2013-02-27
IPC分类号： H05K7/02 , H05K7/06 , H05K7/08 , H05K7/10 , H05K1/02 , H01L23/498 , B81B7/00 , H01L23/00 , H01L23/31
CPC分类号： H05K1/0271 , B81B7/0048 , B81B2207/07 , H01L23/3121 , H01L23/49838 , H01L23/562 , H01L2924/0002 , H01L2924/1433 , H01L2924/3511 , H01L2924/00
摘要： A semiconductor package substrate suitable for supporting a damage-sensitive device, including a substrate core having a first and opposite surface; at least one pair of metal layers covering the first and opposite surfaces of the package substrate core, which define first and opposite metal layer groups, at least one of said layer groups including at least one metal support zone; one pair of solder mask layers covering the outermost metal layers of the at least one pair of metal layers; and a plurality of routing lines; wherein the at least one metal support zone is formed so that it lies beneath at least one side of the base of the damage-sensitive device and so as to occupy a substantial portion of the area beneath the damage-sensitive device which is free of said routing lines; a method for the production of such substrate is also described.
摘要翻译： 一种适用于支撑损伤敏感器件的半导体封装衬底，包括具有第一和相对表面的衬底芯; 覆盖封装衬底芯的第一和相对表面的至少一对金属层，其限定第一和相对的金属层组，所述层组中的至少一个包括至少一个金属支撑区; 一对焊接掩模层，覆盖至少一对金属层的最外层金属层; 和多条路线; 其中所述至少一个金属支撑区域被形成为使得其位于所述损伤敏感装置的所述基部的至少一侧的下方，并且占据所述损伤敏感装置下方的所述区域的大部分，所述损伤敏感装置没有所述 路线; 还描述了制造这种基板的方法。
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8.发明申请公开(公告)号：US20130170166A1
公开(公告)日：2013-07-04
申请号：US13779592
申请日：2013-02-27
IPC分类号： H05K1/02
CPC分类号： H05K1/0271 , B81B7/0048 , B81B2207/07 , H01L23/3121 , H01L23/49838 , H01L23/562 , H01L2924/0002 , H01L2924/1433 , H01L2924/3511 , H01L2924/00
摘要： A semiconductor package substrate suitable for supporting a damage-sensitive device, including a substrate core having a first and opposite surface; at least one pair of metal layers covering the first and opposite surfaces of the package substrate core, which define first and opposite metal layer groups, at least one of said layer groups including at least one metal support zone; one pair of solder mask layers covering the outermost metal layers of the at least one pair of metal layers; and a plurality of routing lines; wherein the at least one metal support zone is formed so that it lies beneath at least one side of the base of the damage-sensitive device and so as to occupy a substantial portion of the area beneath the damage-sensitive device which is free of said routing lines; a method for the production of such substrate is also described.
摘要翻译： 一种适用于支撑损伤敏感器件的半导体封装衬底，包括具有第一和相对表面的衬底芯; 覆盖封装衬底芯的第一和相对表面的至少一对金属层，其限定第一和相对的金属层组，所述层组中的至少一个包括至少一个金属支撑区; 一对焊接掩模层，覆盖至少一对金属层的最外层金属层; 和多条路线; 其中所述至少一个金属支撑区域被形成为使得其位于所述损伤敏感装置的所述基部的至少一侧的下方，并且占据所述损伤敏感装置下方的所述区域的大部分，所述损伤敏感装置没有所述 路线; 还描述了制造这种基板的方法。
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公开(公告)号：US11152289B2
公开(公告)日：2021-10-19
申请号：US16406911
申请日：2019-05-08
IPC分类号： H01L23/495 , H01L23/00 , H01L21/48
摘要： A semiconductor device comprises: a lead-frame comprising a die pad having at least one electrically conductive die pad area an insulating layer applied onto the electrically conductive die pad area. An electrically conductive layer is applied onto the insulating layer with one or more semiconductor dice coupled, for instance adhesively, to the electrically conductive layer. The electrically conductive die pad area, the electrically conductive layer and the insulating layer sandwiched therebetween form at least one capacitor integrated in the device. The electrically conductive die pad area comprises a sculptured structure with valleys and peaks therein; the electrically conductive layer comprises electrically conductive filling material extending into the valleys in the sculptured structure of the electrically conductive die pad area.
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公开(公告)号：US10283441B2
公开(公告)日：2019-05-07
申请号：US15282619
申请日：2016-09-30
IPC分类号： H01L23/495 , H01L21/48 , H01L21/56 , H01L23/31 , H01L49/02
摘要： In an embodiment, a method of integrating capacitors in semiconductor devices includes: providing a lead-frame for a semiconductor device, the lead-frame including one or more electrically conductive areas, forming a dielectric layer over the electrically conductive area or areas, forming an electrically conductive layer over the dielectric layer thus forming one or more capacitors including the dielectric layer sandwiched between an electrically conductive area and the electrically conductive layer, and arranging a semiconductor die onto the lead-frame by providing electrical contact between the semiconductor die and the electrically conductive layer.
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