Invention Grant
- Patent Title: Doric pillar supported maskless airgap structure for capacitance benefit with unlanded via solution
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Application No.: US15574816Application Date: 2015-06-25
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Publication No.: US10593627B2Publication Date: 2020-03-17
- Inventor: Kanwal Jit Singh , Kevin Lin , Robert Lindsey Bristol
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2015/037835 WO 20150625
- International Announcement: WO2016/209246 WO 20161219
- Main IPC: H01L23/532
- IPC: H01L23/532 ; H01L29/06 ; H01L23/522 ; H01L21/768 ; H01L23/498 ; H01L21/764

Abstract:
Embodiments of the invention include interconnect layers with floating interconnect lines and methods of forming such interconnect layers. In an embodiment, a plurality of openings are formed in a first sacrificial material layer. Conductive vias and dielectric pillars may be formed in the openings. A second sacrificial material layer may then be formed over the pillars, the vias, and the first sacrificial material layer. In an embodiment, a permeable etchstop layer is formed over a top surface of the second sacrificial layer. Embodiments then include forming an interconnect line in the second sacrificial material layer. In an embodiment, the first and second sacrificial material layers are removed through the permeable etchstop layer after the interconnect line has been formed. According to an embodiment, the permeable etchstop layer may then be stuffed with a fill material in order to harden the permeable etchstop layer.
Public/Granted literature
- US20180145035A1 DORIC PILLAR SUPPORTED MASKLESS AIRGAP STRUCTURE FOR CAPACITANCE BENEFIT WITH UNLANDED VIA SOLUTION Public/Granted day:2018-05-24
Information query
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