Invention Grant
- Patent Title: Efficient memory layout for enabling smart data compression in machine learning environments
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Application No.: US15682795Application Date: 2017-08-22
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Publication No.: US10600147B2Publication Date: 2020-03-24
- Inventor: Bharat Daga , Ajit Singh , Pradeep Janedula
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Jaffery Watson Mendonsa & Hamilton LLP
- Main IPC: G06K9/00
- IPC: G06K9/00 ; G06T1/60 ; G06T9/00 ; G06T11/40

Abstract:
A mechanism is described for facilitating efficient memory layout for enabling smart data compression in machine learning environments. A method of embodiments, as described herein, includes facilitating dividing an initial tile representing an image into primary multiple tiles such that each tile of the primary multiple tiles is regarded as an independent image as processed by one or more processors of a computing device. The method may further include computing the primary multiple tiles into secondary multiple tiles compatible in size of a local buffer. The method may further include merging the multiple secondary multiple tiles into a final tile representing the image, and compressing the final tile.
Public/Granted literature
- US20190066257A1 EFFICIENT MEMORY LAYOUT FOR ENABLING SMART DATA COMPRESSION IN MACHINE LEARNING ENVIRONMENTS Public/Granted day:2019-02-28
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