公开(公告)号：US10600147B2

公开(公告)日：2020-03-24

申请号：US15682795

申请日：2017-08-22

Applicant: Intel Corporation

Inventor： Bharat Daga ,  Ajit Singh ,  Pradeep Janedula

IPC: G06K9/00 ,  G06T1/60 ,  G06T9/00 ,  G06T11/40

Abstract: A mechanism is described for facilitating efficient memory layout for enabling smart data compression in machine learning environments. A method of embodiments, as described herein, includes facilitating dividing an initial tile representing an image into primary multiple tiles such that each tile of the primary multiple tiles is regarded as an independent image as processed by one or more processors of a computing device. The method may further include computing the primary multiple tiles into secondary multiple tiles compatible in size of a local buffer. The method may further include merging the multiple secondary multiple tiles into a final tile representing the image, and compressing the final tile.

公开(公告)号：US11640537B2

公开(公告)日：2023-05-02

申请号：US16378107

申请日：2019-04-08

Applicant: Intel Corporation

Inventor： Bharat Daga ,  Krishnakumar Nair ,  Pradeep Janedula ,  Aravind Babu Srinivasan ,  Bijoy Pazhanimala ,  Ambili Vengallur

IPC: G06N3/10

Abstract: An apparatus to facilitate execution of non-linear functions operations is disclosed. The apparatus comprises accelerator circuitry including a compute grid having a plurality of processing elements to execute neural network computations, store values resulting from the neural network computations, and perform piecewise linear (PWL) approximations of one or more non-linear functions using the stored values as input data.

公开(公告)号：US10990648B2

公开(公告)日：2021-04-27

申请号：US15670359

申请日：2017-08-07

Applicant: Intel Corporation

Inventor： Pradeep Janedula ,  Bijoy Pazhanimala ,  Bharat Daga ,  Saurabh Dhoble

IPC: G06F17/15 ,  G06F17/16

Abstract: One embodiment provides a compute apparatus to perform machine learning operations, the compute apparatus comprising a hardware accelerator including a compute unit to perform a Winograd convolution, the compute unit configurable to perform the Winograd convolution for a first kernel size using a transform associated with a second kernel size.

公开(公告)号：US20200320403A1

公开(公告)日：2020-10-08

申请号：US16378107

申请日：2019-04-08

Applicant: Intel Corporation

Inventor： Bharat Daga ,  Krishnakumar Nair ,  Pradeep Janedula ,  Aravind Babu Srinivasan ,  Bijoy Pazhanimala ,  Ambili Vengallur

IPC: G06N3/10

Abstract: An apparatus to facilitate execution of non-linear functions operations is disclosed. The apparatus comprises accelerator circuitry including a compute grid having a plurality of processing elements to execute neural network computations, store values resulting from the neural network computations, and perform piecewise linear (PWL) approximations of one or more non-linear functions using the stored values as input data.

公开(公告)号：US10769526B2

公开(公告)日：2020-09-08

申请号：US15960851

申请日：2018-04-24

Applicant: Intel Corporation

Inventor： Bharat Daga ,  Pradeep Janedula ,  Aravind Babu Srinivasan ,  Ambili Vengallur

IPC: G06F7/544 ,  G06F17/16 ,  G06N3/08 ,  G06N3/04 ,  G06N3/063

Abstract: An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises accelerator circuitry including a first set of processing elements to perform first computations including matrix multiplication operations, a second set of processing elements to perform second computations including sum of elements of weights and offset multiply operations and a third set of processing elements to perform third computations including sum of elements of inputs and offset multiply operations, wherein the second and third computations are performed in parallel with the first computations.

公开(公告)号：US20190066257A1

公开(公告)日：2019-02-28

申请号：US15682795

申请日：2017-08-22

Applicant: Intel Corporation

Inventor： Bharat Daga ,  Ajit Singh ,  Pradeep Janedula

IPC: G06T1/60 ,  G06T9/00

Abstract: A mechanism is described for facilitating efficient memory layout for enabling smart data compression in machine learning environments. A method of embodiments, as described herein, includes facilitating dividing an initial tile representing an image into primary multiple tiles such that each tile of the primary multiple tiles is regarded as an independent image as processed by one or more processors of a computing device. The method may further include computing the primary multiple tiles into secondary multiple tiles compatible in size of a local buffer. The method may further include merging the multiple secondary multiple tiles into a final tile representing the image, and compressing the final tile.