Invention Grant
- Patent Title: Layout construction for addressing electromigration
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Application No.: US15927539Application Date: 2018-03-21
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Publication No.: US10600785B2Publication Date: 2020-03-24
- Inventor: Seid Hadi Rasouli , Michael Joseph Brunolli , Christine Sung-An Hau-Riege , Mickael Malabry , Sucheta Kumar Harish , Prathiba Balasubramanian , Kamesh Medisetti , Nikolay Bomshtein , Animesh Datta , Ohsang Kwon
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Arent Fox, LLP and Qualcomm
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/8238 ; H03K17/16 ; H03K17/687 ; H01L23/482 ; H01L27/02 ; H01L23/528 ; H01L23/522

Abstract:
A CMOS device with a plurality of PMOS transistors and a plurality of NMOS transistors includes a first interconnect and a second interconnect on an interconnect level connecting a first subset and a second subset of PMOS drains together, respectively. The first and second subsets are different and the first and second interconnect are disconnected on the interconnect level. A third interconnect and a fourth interconnect on the interconnect level connect a first subset and a second subset of the NMOS drains together, respectively. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, fourth interconnects are coupled together through at least one other interconnect level. Additional interconnects on the interconnect level connect the first and third interconnects together, and the second and fourth interconnects together, to provide parallel current paths with a current path through the at least one other interconnect level.
Public/Granted literature
- US20180211957A1 LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION Public/Granted day:2018-07-26
Information query
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