Invention Grant
- Patent Title: Memory structures having reduced via resistance
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Application No.: US16147264Application Date: 2018-09-28
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Publication No.: US10600844B2Publication Date: 2020-03-24
- Inventor: Anna Maria Conti , Andrea Redaelli
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Thorpe North & Western, LLP
- Agent David W. Osborne
- Main IPC: H01L27/24
- IPC: H01L27/24 ; H01L45/00

Abstract:
A memory structure can include a memory cell, a via, a dielectric material separating the memory cell from the via, a metal ceramic composite material layer on the memory cell and the dielectric material, and a conductive layer on the metal ceramic composite material layer and the via. The conductive layer can be in direct contact with the top surface of the via.
Public/Granted literature
- US20190043924A1 MEMORY STRUCTURES HAVING REDUCED VIA RESISTANCE Public/Granted day:2019-02-07
Information query
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