Invention Grant
- Patent Title: On-die termination architecture
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Application No.: US15790896Application Date: 2017-10-23
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Publication No.: US10606512B2Publication Date: 2020-03-31
- Inventor: Kallol Mazumder , Myung-Ho Bae
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Fletcher Yoder, P.C.
- Main IPC: G06F3/00
- IPC: G06F3/00 ; G06F3/06 ; G11C29/02 ; G11C11/4076 ; G11C7/22 ; G11C11/419

Abstract:
Methods and devices that receive commands at a command interface and uses control circuitry configured to implement the command. A routing pipeline is configured to translate and route the command from the command interface to the control circuitry. The routing pipeline includes clock circuitry. The clock circuitry includes a clock delay line and multiple cloned delay lines derived from the clock delay line. Each of the cloned delay lines are dedicated to a command type of multiple command types. The routing pipeline also includes delay circuitry configured to utilize the cloned delay lines to shift a data pin signal of the semiconductor device or shift a data strobe pin signal of the semiconductor device.
Public/Granted literature
- US20190121577A1 ON-DIE TERMINATION ARCHITECTURE Public/Granted day:2019-04-25
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