公开(公告)号：US10483970B2

公开(公告)日：2019-11-19

申请号：US16200450

申请日：2018-11-26

申请人： Micron Technology, Inc.

发明人： Kallol Mazumder ,  Myung-Ho Bae

IPC分类号： G11C7/00 ,  H03K19/00 ,  H03K3/037 ,  H03K19/20 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096

摘要： Devices and methods include receiving a command at a command interface to assert on-die termination (ODT) during an operation. An indication of a shift mode register value is received via an input. The shift mode register value corresponds to a number of shifts of a rising edge of the command in a backward direction. A delay pipeline delays the received command the number of shifts in the backward direction to generate a shifted rising edge command signal. Combination circuitry is configured to combine a falling edge command signal with the shifted rising edge command signal to form a transformed command.

公开(公告)号：US10470475B2

公开(公告)日：2019-11-12

申请号：US16197871

申请日：2018-11-21

申请人： MICRON TECHNOLOGY, INC.

发明人： Kallol Mazumder ,  Myung-Ho Bae

IPC分类号： G11C7/10 ,  A23C3/07 ,  C02F1/32 ,  A23L2/50 ,  A23L3/28 ,  C02F1/72 ,  A23C9/20 ,  G01N21/94 ,  G01N21/64 ,  G01N21/53 ,  G01N21/33 ,  C02F1/00 ,  G01N33/18 ,  C02F1/28 ,  C02F1/44

摘要： A system includes memory banks that store data and a data path coupled to the memory banks that transfers the data. The system also includes a latch that gates the data path based on a clock signal in the system. The system further includes interface circuitry coupled to the data path that sends an instruction to the memory banks to transmit the data on the data path in response to receiving a first rising edge of the clock signal. The interface circuitry also outputs gated data in response to receiving a second rising edge of the clock signal. The latch gates the data path to store the gated data in response to receiving a falling edge of the clock signal.

公开(公告)号：US20190097630A1

公开(公告)日：2019-03-28

申请号：US16200450

申请日：2018-11-26

申请人： Micron Technology, Inc.

发明人： Kallol Mazumder ,  Myung-Ho Bae

IPC分类号： H03K19/00 ,  G11C11/408 ,  G11C11/4076 ,  H03K3/037 ,  H03K19/20 ,  G11C11/4096

CPC分类号： H03K19/0005 ,  G11C5/148 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/109 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/413 ,  G11C11/417 ,  G11C11/418 ,  G11C11/419 ,  G11C29/022 ,  G11C29/028 ,  G11C29/46 ,  G11C2207/2227 ,  G11C2207/2254 ,  H03K3/037 ,  H03K19/20

摘要： Devices and methods include receiving a command at a command interface to assert on-die termination (ODT) during an operation. An indication of a shift mode register value is received via an input. The shift mode register value corresponds to a number of shifts of a rising edge of the command in a backward direction. A delay pipeline delays the received command the number of shifts in the backward direction to generate a shifted rising edge command signal. Combination circuitry is configured to combine a falling edge command signal with the shifted rising edge command signal to form a transformed command.

公开(公告)号：US20190090499A1

公开(公告)日：2019-03-28

申请号：US16197871

申请日：2018-11-21

申请人： MICRON TECHNOLOGY, INC.

发明人： Kallol Mazumder ,  Myung-Ho Bae

IPC分类号： A23C3/07 ,  A23C9/20 ,  G01N21/64 ,  G01N21/53 ,  G01N21/33 ,  G01N33/18 ,  C02F1/72 ,  C02F1/00 ,  G01N21/94 ,  C02F1/32 ,  A23L2/50 ,  A23L3/28 ,  C02F1/28 ,  C02F1/44

CPC分类号： A23C3/076 ,  A23C9/206 ,  A23L2/50 ,  A23L3/28 ,  A23V2002/00 ,  C02F1/003 ,  C02F1/008 ,  C02F1/283 ,  C02F1/325 ,  C02F1/44 ,  C02F1/725 ,  C02F2201/009 ,  C02F2201/3222 ,  C02F2201/3227 ,  C02F2201/326 ,  C02F2209/001 ,  C02F2209/003 ,  C02F2209/006 ,  C02F2209/008 ,  C02F2209/02 ,  C02F2209/08 ,  C02F2209/11 ,  C02F2209/15 ,  C02F2209/20 ,  C02F2209/21 ,  C02F2303/04 ,  C02F2305/10 ,  C02F2307/02 ,  C02F2307/04 ,  C02F2307/10 ,  G01N21/33 ,  G01N21/53 ,  G01N21/6486 ,  G01N21/94 ,  G01N33/18 ,  G01N2201/062 ,  Y02A20/212 ,  Y02W10/37

摘要： A system includes memory banks that store data and a data path coupled to the memory banks that transfers the data. The system also includes a latch that gates the data path based on a clock signal in the system. The system further includes interface circuitry coupled to the data path that sends an instruction to the memory banks to transmit the data on the data path in response to receiving a first rising edge of the clock signal. The interface circuitry also outputs gated data in response to receiving a second rising edge of the clock signal. The latch gates the data path to store the gated data in response to receiving a falling edge of the clock signal.

公开(公告)号：US10157648B1

公开(公告)日：2018-12-18

申请号：US15652986

申请日：2017-07-18

申请人： MICRON TECHNOLOGY, INC.

发明人： Kallol Mazumder ,  Myung-Ho Bae

IPC分类号： G11C7/10 ,  G11C7/22

摘要： A system includes memory banks that store data and a data path coupled to the memory banks that transfers the data. The system also includes a latch that gates the data path based on a clock signal in the system. The system further includes interface circuitry coupled to the data path that sends an instruction to the memory banks to transmit the data on the data path in response to receiving a first rising edge of the clock signal. The interface circuitry also outputs gated data in response to receiving a second rising edge of the clock signal. The latch gates the data path to store the gated data in response to receiving a falling edge of the clock signal.

公开(公告)号：US10606512B2

公开(公告)日：2020-03-31

申请号：US15790896

申请日：2017-10-23

申请人： Micron Technology, Inc.

发明人： Kallol Mazumder ,  Myung-Ho Bae

IPC分类号： G06F3/00 ,  G06F3/06 ,  G11C29/02 ,  G11C11/4076 ,  G11C7/22 ,  G11C11/419

摘要： Methods and devices that receive commands at a command interface and uses control circuitry configured to implement the command. A routing pipeline is configured to translate and route the command from the command interface to the control circuitry. The routing pipeline includes clock circuitry. The clock circuitry includes a clock delay line and multiple cloned delay lines derived from the clock delay line. Each of the cloned delay lines are dedicated to a command type of multiple command types. The routing pipeline also includes delay circuitry configured to utilize the cloned delay lines to shift a data pin signal of the semiconductor device or shift a data strobe pin signal of the semiconductor device.

公开(公告)号：US20190121577A1

公开(公告)日：2019-04-25

申请号：US15790896

申请日：2017-10-23

申请人： Micron Technology, Inc.

发明人： Kallol Mazumder ,  Myung-Ho Bae

IPC分类号： G06F3/06

摘要： Methods and devices that receive commands at a command interface and uses control circuitry configured to implement the command. A routing pipeline is configured to translate and route the command from the command interface to the control circuitry. The routing pipeline includes clock circuitry. The clock circuitry includes a clock delay line and multiple cloned delay lines derived from the clock delay line. Each of the cloned delay lines are dedicated to a command type of multiple command types. The routing pipeline also includes delay circuitry configured to utilize the cloned delay lines to shift a data pin signal of the semiconductor device or shift a data strobe pin signal of the semiconductor device.

公开(公告)号：US10148269B1

公开(公告)日：2018-12-04

申请号：US15658276

申请日：2017-07-24

申请人： Micron Technology, Inc.

发明人： Kallol Mazumder ,  Myung-Ho Bae

IPC分类号： H03K19/00 ,  H03K3/037 ,  H03K19/20 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096

摘要： Devices and methods include receiving a command at a command interface to assert on-die termination (ODT) during an operation. An indication of a shift mode register value is received via an input. The shift mode register value corresponds to a number of shifts of a rising edge of the command in a backward direction. A delay pipeline delays the received command the number of shifts in the backward direction to generate a shifted rising edge command signal. Combination circuitry is configured to combine a falling edge command signal with the shifted rising edge command signal to form a transformed command.