Invention Grant
- Patent Title: Wafer level integration including design/co-design, structure process, equipment stress management and thermal management
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Application No.: US16289800Application Date: 2019-03-01
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Publication No.: US10651134B2Publication Date: 2020-05-12
- Inventor: Jeffrey Gelorme , Li-Wen Hung , John U. Knickerbocker
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Fleit Intellectual Property Law
- Agent Donna Flores
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L25/065 ; H01L21/768 ; H01L25/00
Abstract:
A method of manufacturing a multi-layer wafer is provided. At least one stress compensating polymer layer is applied to at least one of two heterogeneous wafers. The stress compensating polymer layer is low temperature bonded to the other of the two heterogeneous wafers to form a multi-layer wafer pair. Channels are created between die on at least one of the two heterogeneous wafers. The channels are back filled with one of oxide or polymer to create a channel oxide deposition.
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