Invention Grant
- Patent Title: Down-mode valley-current-sense replica linearization
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Application No.: US16292750Application Date: 2019-03-05
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Publication No.: US10651742B2Publication Date: 2020-05-12
- Inventor: Stefan Dietrich , Joerg Kirchner
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Lawrence J. Bassuk; Charles A. Brill; Frank D. Cimino
- Main IPC: H02M3/158
- IPC: H02M3/158 ; H03K5/24 ; H03K17/687 ; H02M1/00

Abstract:
A current measurement linearization circuit for a DC/DC boost converter includes a back-gate sensing transistor and a back-gate reset transistor. The back-gate sensing transistor has a first terminal coupled to a first body contact of a high-side power transistor and a second terminal coupled to a second body contact of a first replica transistor in a valley-current sensing circuit. The back-gate reset transistor has a first terminal coupled to a max reference voltage that is equal to the greater of an input voltage and an output voltage and a second terminal coupled to the second body contact.
Public/Granted literature
- US20200076308A1 DOWN-MODE VALLEY-CURRENT-SENSE REPLICA LINEARIZATION Public/Granted day:2020-03-05
Information query
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