Invention Grant
- Patent Title: Method for fabricating a semiconductor structure on a semiconductor wafer
-
Application No.: US16039284Application Date: 2018-07-18
-
Publication No.: US10658173B2Publication Date: 2020-05-19
- Inventor: Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen , Ching-Pin Hsu
- Applicant: UNITED MICROELECTRONICS CORP. , Fujian Jinhua Integrated Circuit Co., Ltd.
- Applicant Address: TW Hsin-Chu CN Quanzhou, Fujian Province
- Assignee: UNITED MICROELECTRONICS CORP.,Fujian Jinhua Integrated Circuit Co., Ltd.
- Current Assignee: UNITED MICROELECTRONICS CORP.,Fujian Jinhua Integrated Circuit Co., Ltd.
- Current Assignee Address: TW Hsin-Chu CN Quanzhou, Fujian Province
- Agent Winston Hsu
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@19dcddc5
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L21/3213 ; H01L21/67 ; H01L21/3065 ; H01L27/108
Abstract:
A method for fabricating a semiconductor structure on a semiconductor wafer is disclosed. A semiconductor wafer having a first region, a second region, and a wafer bevel region is provided. The wafer bevel region has a silicon surface. A first semiconductor structure is formed in the first region and a second semiconductor structure is formed in the second region. The semiconductor wafer is subjected to a bevel plasma treatment to form a blocking layer only in the wafer bevel region. A silicidation process is then performed to form a silicide layer only in the first region and the second region.
Public/Granted literature
- US20200020524A1 METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE ON A SEMICONDUCTOR WAFER Public/Granted day:2020-01-16
Information query
IPC分类:
