Invention Grant
- Patent Title: Methods of forming stacked SOI semiconductor devices with back bias mechanism
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Application No.: US16414203Application Date: 2019-05-16
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Publication No.: US10658388B2Publication Date: 2020-05-19
- Inventor: Bartlomiej Pawlak
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Main IPC: H01L27/01
- IPC: H01L27/01 ; H01L27/12 ; H01L29/786 ; H01L21/84 ; H01L29/06 ; H01L21/8234 ; H01L29/66 ; H01L21/822 ; H01L27/06

Abstract:
A method includes forming a first circuit element in and above a first semiconductor layer, the first semiconductor layer being formed on a first buried insulating layer, forming drain and source regions of the first circuit element at least partially in the first semiconductor layer, and forming a layer stack above the first circuit element, the layer stack including a conductive layer, a second buried insulating layer formed above the conductive layer, and a second semiconductor layer formed above the second buried insulating layer, wherein the conductive layer is electrically isolated from the drain and source regions.
Public/Granted literature
- US20190280010A1 METHODS OF FORMING STACKED SOI SEMICONDUCTOR DEVICES WITH BACK BIAS MECHANISM Public/Granted day:2019-09-12
Information query
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