Invention Grant
- Patent Title: Multi-node system low power management
-
Application No.: US15850261Application Date: 2017-12-21
-
Publication No.: US10671148B2Publication Date: 2020-06-02
- Inventor: Benjamin Tsien , Bryan P. Broussard , Vydhyanathan Kalyanasundharam
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Kowert Hood Munyon Rankin and Goetzel PC
- Agent Rory D. Rankin
- Main IPC: G06F1/3296
- IPC: G06F1/3296 ; G06F13/26 ; G06F12/0831 ; G06F1/3234

Abstract:
Systems, apparatuses, and methods for performing efficient power management for a multi-node computing system are disclosed. A computing system including multiple nodes utilizes a non-uniform memory access (NUMA) architecture. A first node receives a broadcast probe from a second node. The first node spoofs a miss response for a powered down third node, which prevents the third node from waking up to respond to the broadcast probe. Prior to powering down, the third node flushed its probe filter and caches, and updated its system memory with the received dirty cache lines. The computing system includes a master node for storing interrupt priorities of the multiple cores in the computing system for arbitrated interrupts. The cores store indications of fixed interrupt identifiers for each core in the computing system. Arbitrated and fixed interrupts are handled by cores with point-to-point unicast messages, rather than broadcast messages.
Public/Granted literature
- US20190196574A1 MULTI-NODE SYSTEM LOW POWER MANAGEMENT Public/Granted day:2019-06-27
Information query