Invention Grant
- Patent Title: Methods and systems for performing decoding in finFET based memories
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Application No.: US16166647Application Date: 2018-10-22
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Publication No.: US10672443B2Publication Date: 2020-06-02
- Inventor: Ankur Gupta , Abhishek Kesarwani , Parvinder Kumar Rana , Manish Chandra Joshi , Lava Kumar Pulluru
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si
- Agency: Sughrue Mion, PLLC
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@375be3eb
- Main IPC: G11C8/10
- IPC: G11C8/10 ; G11C7/22 ; G11C8/06 ; G11C8/08 ; G11C17/12 ; G11C11/418 ; G11C11/417

Abstract:
A fin-Field Effect Transistor based system on chip (SoC) memory is provided and includes a control block, first logic gates, and row decoder blocks. The control block includes a clock generator circuit that generates an internal clock signal, and a global driver circuit coupled to the clock generator circuit that drives a global clock signal. Each row decoder block includes a second logic gate that receives higher order non-clocked address signals via input terminals, a transmission gate that combines the global clock signal and the higher order non-clocked address signals, third logic gates that receive lower order non-clocked address signals and higher order clocked address signals, and output a combined lower order address and higher order address along with the global clock signal, level shifter circuits that receive the outputs, and word-line driver circuits that generate word-lines based on the output of the level shifter circuits.
Public/Granted literature
- US20200075070A1 METHODS AND SYSTEMS FOR PERFORMING DECODING IN FINFET BASED MEMORIES Public/Granted day:2020-03-05
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