Invention Grant
- Patent Title: Systems enabling lower-stress processing of semiconductor device structures and related structures
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Application No.: US16244939Application Date: 2019-01-10
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Publication No.: US10679967B2Publication Date: 2020-06-09
- Inventor: Andrew M. Bayless , Joseph M. Brand
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/683

Abstract:
Semiconductor device assemblies may include a carrier wafer and a thermoset adhesive on a surface of the carrier wafer. A metal barrier material may be located on the thermoset adhesive. A thermoplastic adhesive may be located on an opposite side of the metal barrier material from the thermoset adhesive. A device wafer may be located on an opposite side of the thermoplastic material from the metal barrier material. Semiconductor device processing systems may include a carrier wafer having a thermoset adhesive adhered to a surface thereof and a metal barrier material adhered to the thermoset adhesive opposite the carrier wafer. A laser apparatus may be located on an opposite side of the carrier wafer from the metal barrier material and positioned to aim a laser beam through the carrier wafer to impinge on the metal barrier material.
Public/Granted literature
- US20190148335A1 SYSTEMS ENABLING LOWER-STRESS PROCESSING OF SEMICONDUCTOR DEVICE STRUCTURES AND RELATED STRUCTURES Public/Granted day:2019-05-16
Information query
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