公开(公告)号：US20250132279A1

公开(公告)日：2025-04-24

申请号：US18790320

申请日：2024-07-31

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Andrew M. Bayless ,  Owen R. Fay

IPC: H01L23/00

Abstract: A semiconductor device is presented. The semiconductor device includes a lower semiconductor die, a stack of upper semiconductor dies disposed over the lower semiconductor die, a non-conductive film material disposed between adjacent semiconductor dies of the lower semiconductor die and the stack of upper semiconductor dies, and an epoxy material disposed on at least one sidewall of the stack of upper semiconductor dies, wherein the epoxy material has a different material composition to the NCF material.

公开(公告)号：US20250015000A1

公开(公告)日：2025-01-09

申请号：US18893435

申请日：2024-09-23

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Andrew M. Bayless

IPC: H01L23/532 ,  H01L21/78 ,  H01L23/31 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065

Abstract: Semiconductor dies with edges protected and methods for generating the semiconductor dies are disclosed. Further, the disclosed methods provide for separating the semiconductor dies without using a dicing technique. In one embodiment, trenches are formed on a front side of a substrate including semiconductor dies. Individual trenches correspond to scribe lines of the substrate where each trench has a depth greater than a final thickness of the semiconductor dies. A composite layer may be formed on sidewalls of the trenches to protect the edges of the semiconductor dies. The composite layer includes a metallic layer that shields the semiconductor dies from electromagnetic interference. Subsequently, the substrate may be thinned from a back side to singulate individual semiconductor dies from the substrate.

公开(公告)号：US20230420300A1

公开(公告)日：2023-12-28

申请号：US18243664

申请日：2023-09-08

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L21/78 ,  H01L21/50 ,  H01L21/683 ,  H01L21/67

CPC classification number: H01L21/78 ,  H01L21/50 ,  H01L21/6836 ,  H01L21/67051 ,  H01L2221/68322 ,  H01L2221/68327 ,  H01L21/6708

Abstract: Methods for releasing thinned semiconductor dies from a mount tape and associated apparatuses are disclosed. In one embodiment, a sacrificial layer may be disposed at a back side of thinned substrate including semiconductor dies. The sacrificial layer includes materials soluble in contact with a fluid (and/or vapor). A sheet of perforated mount tape may be attached to the sacrificial layer and an ejection component may be provided under a target semiconductor die to be released. The ejection component is configured to create a locally confined puddle of the fluid under the target semiconductor die such that the sacrificial layer is removed to release the target semiconductor die from the mount tape. Further, a support component may be provided to pick up the target semiconductor die after the target semiconductor die is released from the mount tape.

公开(公告)号：US11791212B2

公开(公告)日：2023-10-17

申请号：US16713309

申请日：2019-12-13

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L21/78 ,  H01L21/50 ,  H01L21/683 ,  H01L21/67

CPC classification number: H01L21/78 ,  H01L21/50 ,  H01L21/67051 ,  H01L21/6836 ,  H01L21/6708 ,  H01L2221/68322 ,  H01L2221/68327

Abstract: Methods for releasing thinned semiconductor dies from a mount tape and associated apparatuses are disclosed. In one embodiment, a sacrificial layer may be disposed at a back side of thinned substrate including semiconductor dies. The sacrificial layer includes materials soluble in contact with a fluid (and/or vapor). A sheet of perforated mount tape may be attached to the sacrificial layer and an ejection component may be provided under a target semiconductor die to be released. The ejection component is configured to create a locally confined puddle of the fluid under the target semiconductor die such that the sacrificial layer is removed to release the target semiconductor die from the mount tape. Further, a support component may be provided to pick up the target semiconductor die after the target semiconductor die is released from the mount tape.

公开(公告)号：US11776908B2

公开(公告)日：2023-10-03

申请号：US17231210

申请日：2021-04-15

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Andrew M. Bayless

IPC: H01L23/48 ,  H01L23/532 ,  H01L25/00 ,  H01L23/31 ,  H01L21/78 ,  H01L25/065

CPC classification number: H01L23/53238 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50

Abstract: Semiconductor dies with edges protected and methods for generating the semiconductor dies are disclosed. Further, the disclosed methods provide for separating the semiconductor dies without using a dicing technique. In one embodiment, trenches are formed on a front side of a substrate including semiconductor dies. Individual trenches correspond to scribe lines of the substrate where each trench has a depth greater than a final thickness of the semiconductor dies. A composite layer may be formed on sidewalls of the trenches to protect the edges of the semiconductor dies. The composite layer includes a metallic layer that shields the semiconductor dies from electromagnetic interference. Subsequently, the substrate may be thinned from a back side to singulate individual semiconductor dies from the substrate.

公开(公告)号：US20220375893A1

公开(公告)日：2022-11-24

申请号：US17817803

申请日：2022-08-05

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/065

Abstract: This patent application relates to methods and apparatus for temperature modification within a stack of microelectronic devices for mutual collective bonding of the microelectronic devices, and to related substrates and assemblies.

公开(公告)号：US20220013401A1

公开(公告)日：2022-01-13

申请号：US16923754

申请日：2020-07-08

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Andrew M. Bayless

IPC: H01L21/683 ,  H01L23/48 ,  H01L21/48

Abstract: Methods for protecting edges of semiconductor dies are disclosed. Further, the disclosed methods provide for separating the semiconductor dies without using a dicing technique. In one embodiment, a plurality of trenches may be formed on a front side of a substrate including a plurality of semiconductor dies. Individual trenches may correspond to scribe lines of the substrate where each trench includes a depth greater than a final thickness of the semiconductor dies. A dielectric layer may be formed on sidewalls of the trenches, thereby protecting the edges of the semiconductor dies, prior to filling the trenches with an adhesive material. Subsequently, the substrate may be thinned from a back side such that the adhesive material in the trenches may be exposed from the back side. The adhesive material may be removed to singulate individual semiconductor dies of the plurality from the substrate.

公开(公告)号：US11195740B2

公开(公告)日：2021-12-07

申请号：US16386517

申请日：2019-04-17

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Kyle K. Kirby

IPC: H01L21/683 ,  H01L23/48 ,  H01L21/306

Abstract: An assembly comprising a device wafer received in a recess of a carrier wafer. A device wafer comprising a protrusion terminating at an active surface bearing integrated circuitry, the protrusion surrounded by a peripheral flat extending to an outer periphery of the device wafer. A method of wafer thinning using the previously described carrier wafer and device wafer. Various implementations of a carrier wafer having a recess are also disclosed, as are methods of fabrication.

公开(公告)号：US11189590B2

公开(公告)日：2021-11-30

申请号：US16715594

申请日：2019-12-16

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L23/00 ,  H01L21/78 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L23/29

Abstract: Processes for adjusting dimensions of dielectric bond line materials in stacks of microelectronic components to prevent extrusion of the dielectric bond line materials beyond component peripheries during thermocompression bonding by patterning the materials with boundary portions inset from component peripheries, or employing an inset dielectric material surrounded by another solidified dielectric material. Related material films, articles and assemblies are also disclosed.

公开(公告)号：US20200335379A1

公开(公告)日：2020-10-22

申请号：US16386517

申请日：2019-04-17

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Kyle K. Kirby

IPC: H01L21/683 ,  H01L21/306 ,  H01L23/48

Abstract: An assembly comprising a device wafer received in a recess of a carrier wafer. A device wafer comprising a protrusion terminating at an active surface bearing integrated circuitry, the protrusion surrounded by a peripheral flat extending to an outer periphery of the device wafer. A method of wafer thinning using the previously described carrier wafer and device wafer. Various implementations of a carrier wafer having a recess are also disclosed, as are methods of fabrication.