Invention Grant
- Patent Title: Post-compile cache blocking analyzer
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Application No.: US15921813Application Date: 2018-03-15
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Publication No.: US10684833B2Publication Date: 2020-06-16
- Inventor: Ruchira Sasanka , Karthik Raman , Konstantinos Krommydas
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Jordan IP Law, LLC
- Main IPC: G06F8/41
- IPC: G06F8/41 ; G06F9/38
Abstract:
An embodiment of a semiconductor package apparatus may include technology to identify a nested loop in a set of executable instructions, and determine at runtime if the nested loop is a candidate for cache blocking. Other embodiments are disclosed and claimed.
Public/Granted literature
- US20190042225A1 POST-COMPILE CACHE BLOCKING ANALYZER Public/Granted day:2019-02-07
Information query
