Invention Grant
- Patent Title: Multi-level hierarchical routing matrices for pattern-recognition processors
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Application No.: US15137877Application Date: 2016-04-25
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Publication No.: US10684983B2Publication Date: 2020-06-16
- Inventor: Harold B Noyes , David R. Brown
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Fletcher Yoder, P.C.
- Main IPC: G06F15/80
- IPC: G06F15/80 ; H03K19/17728 ; G06F16/903 ; G06K9/00 ; G06N5/00
Abstract:
Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition processor.
Public/Granted literature
- US20160239462A1 MULTI-LEVEL HIERARCHICAL ROUTING MATRICES FOR PATTERN-RECOGNITION PROCESSORS Public/Granted day:2016-08-18
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