A capacitor includes first conductive fingers interdigitated with second conductive fingers at an Mx interconnect level, and third conductive fingers interdigitated with fourth conductive fingers at an Mx-1 interconnect level. The third conductive fingers are offset from the first conductive fingers. The second conductive fingers are offset from the fourth conductive fingers. The capacitor further includes fifth conductive fingers interdigitated with sixth conductive fingers at an Mx-2 interconnect level. The fifth conductive fingers are offset from the third conductive fingers. The sixth conductive fingers are offset from the fourth conductive fingers. The capacitor further includes seventh conductive fingers interdigitated with eighth conductive fingers at an Mx-3 interconnect level. The seventh conductive fingers are offset from the fifth conductive fingers. The eighth conductive fingers are offset from the sixth conductive fingers. A first set of vias electrically couples the first conductive fingers to the fifth conductive fingers.