公开(公告)号：US11257917B2

公开(公告)日：2022-02-22

申请号：US16893993

申请日：2020-06-05

Applicant: QUALCOMM Incorporated

Inventor： Jun Yuan ,  Peijie Feng ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/06

Abstract: Gate-all-around (GAA) transistors with an additional bottom channel for reduced parasitic capacitance and methods of fabricating the same include one or more channels positioned between a source region and a drain region. The one or more channels, which may be nanowire or nanoslab semiconductors, are surrounded by gate material. The GAA transistor further includes an additional semiconductor channel between a bottom section of a gate material and a silicon on insulator (SOI) substrate in a GAA transistor. This additional channel, sometimes referred to as a bottom channel, may be thinner than other channels in the GAA transistor and may have a thickness less than its length.

公开(公告)号：US20200303550A1

公开(公告)日：2020-09-24

申请号：US16895909

申请日：2020-06-08

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Kern Rim ,  Da Yang ,  Peijie Feng

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/165

Abstract: Cell circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation and related methods are disclosed. In one aspect, a cell circuit includes a substrate of semiconductor material and a semiconductor channel structure(s) of a second semiconductor material disposed on the substrate. The semiconductor material applies a stress to the formed semiconductor channel structure(s) to induce a strain in the semiconductor channel structure(s) for increasing carrier mobility. A diffusion break comprising a dielectric material extends through a surrounding structure of an interlayer dielectric, and the semiconductor channel structure(s) and at least a portion of the substrate. The relaxation of strain in areas of the semiconductor channel structure(s) adjacent to the diffusion break is reduced or avoided, because the semiconductor channel structure(s) is constrained by the surrounding structure.

公开(公告)号：US20170170268A1

公开(公告)日：2017-06-15

申请号：US15367320

申请日：2016-12-02

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Peijie Feng ,  Kern Rim ,  Jeffrey Junhao Xu ,  Choh Fei Yeap

IPC: H01L29/06 ,  H01L21/324 ,  H01L27/088 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/02603 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/78696

Abstract: Nanowire metal-oxide semiconductor (MOS) Field-Effect Transistors (FETs) (MOSFETs) employing a nanowire channel structure having rounded nanowire structures is disclosed. To reduce the distance between adjacent nanowire structures to reduce parasitic capacitance while providing sufficient gate control of the channel, the nanowire channel structure employs rounded nanowire structures. For example, the rounded nanowire structures provide for a decreased height from a center area of the rounded nanowire structures to end areas of the rounded nanowire structures. Gate material is disposed around rounded ends of the rounded nanowire structures to extend into a portion of separation areas between adjacent nanowire structures. The gate material extends in the separation areas between adjacent nanowire structures sufficient to create a fringing field to the channel where gate material is not adjacently disposed, to provide strong gate control of the channel even though gate material does not completely surround the rounded nanowire structures.

公开(公告)号：US20240429300A1

公开(公告)日：2024-12-26

申请号：US18339349

申请日：2023-06-22

Applicant: QUALCOMM Incorporated

Inventor： Shreesh Narasimha ,  Yan Sun ,  Peijie Feng

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A gate-all-around (GAA) field effect transistor (FET) device, and related fabrication methods are disclosed. The GAA FET device includes P-type semiconductor PFET(s) and N-type semiconductor NFET(s) having channels with different crystalline orientation through a substrate. The GAA PFET(s) includes a channel structure of a first type of crystalline orientation (e.g., or ) and the GAA NFET(s) include a channel structure of a second type of crystalline orientation (e.g., ) different from the first type of crystalline orientation of the GAA PFET(s). The different crystalline orientation channels improve the balance of carrier mobility for both carrier types (i.e., P-type and N-type) of GAA FETs in the GAA FET device. In one aspect, the different crystalline orientation channels are provided through a substrate to increase and/or balance carrier mobility between GAA PFET(s) and NFET(s) to achieve a more balanced drive strength between these types of transistors.

公开(公告)号：US10686031B2

公开(公告)日：2020-06-16

申请号：US15937097

申请日：2018-03-27

Applicant: QUALCOMM Incorporated

Inventor： Peijie Feng ,  Junjing Bao ,  Ye Lu ,  Giridhar Nallapati

IPC: H01L49/02 ,  H01L23/522

Abstract: A capacitor includes first conductive fingers interdigitated with second conductive fingers at an Mx interconnect level, and third conductive fingers interdigitated with fourth conductive fingers at an Mx-1 interconnect level. The third conductive fingers are offset from the first conductive fingers. The second conductive fingers are offset from the fourth conductive fingers. The capacitor further includes fifth conductive fingers interdigitated with sixth conductive fingers at an Mx-2 interconnect level. The fifth conductive fingers are offset from the third conductive fingers. The sixth conductive fingers are offset from the fourth conductive fingers. The capacitor further includes seventh conductive fingers interdigitated with eighth conductive fingers at an Mx-3 interconnect level. The seventh conductive fingers are offset from the fifth conductive fingers. The eighth conductive fingers are offset from the sixth conductive fingers. A first set of vias electrically couples the first conductive fingers to the fifth conductive fingers.

公开(公告)号：US20200058792A1

公开(公告)日：2020-02-20

申请号：US16104522

申请日：2018-08-17

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Kern Rim ,  Da Yang ,  Peijie Feng

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L29/165 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/66

Abstract: Cell circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation and related methods are disclosed. In one aspect, a cell circuit includes a substrate of semiconductor material and a semiconductor channel structure(s) of a second semiconductor material disposed on the substrate. The semiconductor material applies a stress to the formed semiconductor channel structure(s) to induce a strain in the semiconductor channel structure(s) for increasing carrier mobility. A diffusion break comprising a dielectric material extends through a surrounding structure of an interlayer dielectric, and the semiconductor channel structure(s) and at least a portion of the substrate. The relaxation of strain in areas of the semiconductor channel structure(s) adjacent to the diffusion break is reduced or avoided, because the semiconductor channel structure(s) is constrained by the surrounding structure.

公开(公告)号：US11855198B2

公开(公告)日：2023-12-26

申请号：US16844479

申请日：2020-04-09

Applicant: QUALCOMM Incorporated

Inventor： Chenjie Tang ,  Ye Lu ,  Peijie Feng ,  Junjing Bao

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/42316 ,  H01L29/66462

Abstract: A multi-gate HEMT includes at least two gates, with at least one recessed the same depth or at a deeper depth in a barrier layer than at least one other gate. Recessing a gate decreases the thickness of the barrier layer beneath the gate, reducing a density of high mobility carriers in a two-dimensional electron gas layer (2DEG) conductive channel formed at the heterojunction of a barrier layer and a buffer layer below the recessed gate. The recessed gate can increase gate control of the 2DEG conductive channel. The multi-gate HEMT has at least one gate recessed the same depth or a deeper depth into the buffer layer than another gate, which forms at least two different turn-on voltages for different gates. This can achieve improvement of transconductance linearity and a positive shift of the threshold voltage.

公开(公告)号：US11437379B2

公开(公告)日：2022-09-06

申请号：US17025211

申请日：2020-09-18

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Deepak Sharma ,  Bharani Chava ,  Hyeokjin Lim ,  Peijie Feng ,  Seung Hyuk Kang ,  Jonghae Kim ,  Periannan Chidambaram ,  Kern Rim ,  Giridhar Nallapati ,  Venugopal Boynapalli ,  Foua Vang

IPC: H01L21/336 ,  H01L29/66 ,  H01L27/095 ,  H01L23/528 ,  H01L29/78 ,  H03K19/0185

Abstract: Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.

公开(公告)号：US11387335B2

公开(公告)日：2022-07-12

申请号：US17061709

申请日：2020-10-02

Applicant: QUALCOMM Incorporated

Inventor： Junjing Bao ,  Jun Yuan ,  Peijie Feng

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/423 ,  H01L21/768 ,  H01L21/3213 ,  H01L29/45

Abstract: Disclosed are optimized contract structures and fabrication techniques thereof. At least one aspect includes a semiconductor die. The semiconductor die includes a substrate and a contact disposed within the substrate. The contact includes a first portion with a first vertical cross-section having a first cross-sectional area. The first vertical cross-section has a first width and a first height. The contact also includes a second portion with a second vertical cross-section having a second cross-sectional area less than the first cross-sectional area. The second vertical cross-section includes a lower portion having the first width and a second height less than the first height, and an upper portion disposed above the lower portion and having a second width less than the first width and having a third height less than the first height.

公开(公告)号：US11380685B2

公开(公告)日：2022-07-05

申请号：US17061941

申请日：2020-10-02

Applicant: QUALCOMM Incorporated

Inventor： Junjing Bao ,  Ye Lu ,  Chenjie Tang ,  Peijie Feng

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L27/092

Abstract: Certain aspects of the present disclosure relate to a semiconductor device (e.g., a gate-all-around (GAA) semiconductor device) comprising at least one superlattice fin. One example superlattice fin includes a first plurality of nanosheets composed of a first semiconductor material and a second plurality of nanosheets composed of a second semiconductor material, the second semiconductor material being different from the first semiconductor material, wherein a width of a first nanosheet in the first plurality of nanosheets differs from a width of a second nanosheet in the second plurality of nanosheets, the second nanosheet being adjacent to the first nanosheet.