Invention Grant
- Patent Title: Gate for an enhancement-mode transistor
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Application No.: US16050776Application Date: 2018-07-31
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Publication No.: US10686052B2Publication Date: 2020-06-16
- Inventor: Steve Stoffels
- Applicant: IMEC VZW
- Applicant Address: BE Leuven
- Assignee: IMEC VZW
- Current Assignee: IMEC VZW
- Current Assignee Address: BE Leuven
- Agency: McDonnell Boehnen Hulbert & Berghoff LLP
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@4ff977c9
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/778 ; H01L29/20 ; H01L29/10 ; H01L21/02 ; H01L21/285 ; H01L29/47

Abstract:
An enhancement-mode transistor and method for forming a gate of an enhancement-mode transistor are provided. The method includes: (a) providing a p-doped AlxGayInzN gate layer, consisting of a first part and a second part on top of the first part, above a p-doped Alx′Gay′Inz′N channel layer of an enhancement-mode transistor under construction; and (b) providing a metal gate layer on the top surface of the second part, the metal gate layer being formed of a material such as to form a Schottky barrier with the second part, wherein providing the p-doped AlxGayInzN gate layer comprises the steps of: (a1) growing the first part above the p-doped Alx′Gay′Inz′N channel layer of the enhancement-mode transistor under construction, the first part having an average Mg concentration of at most 3×1019 atoms/cm3, and (a2) growing the second part on the first part, the second part having an average Mg concentration higher than 3×1019 atoms/cm3 and having a top surface having a Mg concentration higher than 6×1019 atoms/cm3.
Public/Granted literature
- US20190051732A1 Gate for an Enhancement-Mode Transistor Public/Granted day:2019-02-14
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