公开(公告)号：US11380789B2

公开(公告)日：2022-07-05

申请号：US16750711

申请日：2020-01-23

Applicant: IMEC VZW

Inventor： Steve Stoffels ,  Stefaan Decoutere

IPC: H01L29/78 ,  H01L29/778 ,  H01L21/8252 ,  H01L29/20

Abstract: A vertical power device is disclosed, the device having a top side and a bottom side, and the device comprising (i) a substrate; (ii) a layered group III-Nitride based device stack formed atop the substrate; (iii) a first vertical group III-Nitride based device and a second vertical group III-Nitride based device formed in the group III-Nitride based device stack, wherein the first vertical group III-Nitride based device and the second vertical group III-Nitride based device are electrically connected; and (iv) a first vertical device isolation structure that isolates the first vertical group III-Nitride based device from the second vertical group III-Nitride based device. Also disclosed are a vertical power system integrating vertical power devices and a process for fabricating a vertical power device.

公开(公告)号：US11094629B2

公开(公告)日：2021-08-17

申请号：US16726120

申请日：2019-12-23

Applicant: IMEC VZW

Inventor： Stefaan Decoutere ,  Steve Stoffels

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/48 ,  H01L23/64 ,  H01L29/20 ,  H01L21/8258 ,  H01L27/06 ,  H01L23/367 ,  H01L23/528

Abstract: A three-dimensional (3D) power device having a plurality of layers that are stacked on top of each other and insulated from each other by interlayers, the plurality of layers comprising a lower layer comprising electrical and thermal conductors; a group III-Nitride based device layer formed above the lower layer, the group III-Nitride based device layer comprising at least one group III-Nitride based power device; a control layer formed above the group III-Nitride based device layer, the control layer comprising at least one control device; and a redistribution layer in between the group III-Nitride based device layer and the control layer, the current redistribution layer comprising a metal pattern being provided for laterally redistributing electrical currents and/or heat.

公开(公告)号：US20200243678A1

公开(公告)日：2020-07-30

申请号：US16750711

申请日：2020-01-23

Applicant: IMEC VZW

Inventor： Steve Stoffels ,  Stefaan Decoutere

IPC: H01L29/78 ,  H01L21/8252 ,  H01L29/778

Abstract: A vertical power device is disclosed, the device having a top side and a bottom side, and the device comprising (i) a substrate; (ii) a layered group III-Nitride based device stack formed atop the substrate; (iii) a first vertical group III-Nitride based device and a second vertical group III-Nitride based device formed in the group III-Nitride based device stack, wherein the first vertical group III-Nitride based device and the second vertical group III-Nitride based device are electrically connected; and (iv) a first vertical device isolation structure that isolates the first vertical group III-Nitride based device from the second vertical group III-Nitride based device. Also disclosed are a vertical power system integrating vertical power devices and a process for fabricating a vertical power device.

公开(公告)号：US20170263700A1

公开(公告)日：2017-09-14

申请号：US15452955

申请日：2017-03-08

Applicant: IMEC VZW

Inventor： Steve Stoffels ,  Yoganand Saripalli

IPC: H01L29/06 ,  H01L29/205 ,  H01L29/861 ,  H01L21/225 ,  H01L21/306 ,  H01L21/285 ,  H01L21/324 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/0634 ,  H01L21/2258 ,  H01L21/28575 ,  H01L21/30612 ,  H01L21/3245 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/861

Abstract: The present disclosure is related to a III-Nitride semiconductor device comprising a base substrate, a buffer layer, a channel layer, a barrier layer so that a 2-dimensional charge carrier gas is formed or can be formed near the interface between the channel layer and the barrier layer, and at least one set of a first and second electrode in electrical contact with the 2-dimensional charge carrier gas, wherein the device further comprises a mobile charge layer (MCL) within the buffer layer or near the interface between the buffer layer and the channel layer, when the device is in the on-state. The device further comprises an electrically conductive path between one of the electrodes and the mobile charge layer. The present disclosure is also related to a method for producing a device according to the present disclosure.

公开(公告)号：US11664223B2

公开(公告)日：2023-05-30

申请号：US17062192

申请日：2020-10-02

Applicant: IMEC VZW

Inventor： Steve Stoffels ,  Hu Liang

IPC: H01L21/02

CPC classification number: H01L21/02639 ,  H01L21/0254 ,  H01L21/02458 ,  H01L21/02576 ,  H01L21/02598 ,  H01L21/02609

Abstract: A method for manufacturing an III-nitride semiconductor structure is provided. The method includes providing a substrate comprising a first layer having an upper surface of monocrystalline III-nitride material; providing, over the upper surface, a patterned dielectric layer comprising a first dielectric feature; loading the substrate into a process chamber; exposing the substrate to a first gas mixture comprising at least one Group III-metal organic precursor gas, a nitrogen containing gas and hydrogen gas at a predetermined temperature, thereby forming, on the upper surface, a second layer of a monocrystalline III-nitride material by area selective growth wherein two opposing sidewalls of the dielectric feature are oriented parallel to one of the {11-20} crystal planes of the first layer such that upon formation of the second layer of the monocrystalline III-nitride material, a first trench having tapered sidewalls is formed so that the crystal plane of the second layer parallel to the tapered sidewalls is one of the {1-101} crystal planes.

公开(公告)号：US20210118680A1

公开(公告)日：2021-04-22

申请号：US17062192

申请日：2020-10-02

Applicant: IMEC VZW

Inventor： Steve Stoffels ,  Hu Liang

IPC: H01L21/02

Abstract: A method for manufacturing an III-nitride semiconductor structure is provided. The method includes providing a substrate comprising a first layer having an upper surface of monocrystalline III-nitride material; providing, over the upper surface, a patterned dielectric layer comprising a first dielectric feature; loading the substrate into a process chamber; exposing the substrate to a first gas mixture comprising at least one Group III-metal organic precursor gas, a nitrogen containing gas and hydrogen gas at a predetermined temperature, thereby forming, on the upper surface, a second layer of a monocrystalline III-nitride material by area selective growth wherein two opposing sidewalls of the dielectric feature are oriented parallel to one of the {11-20} crystal planes of the first layer such that upon formation of the second layer of the monocrystalline III-nitride material, a first trench having tapered sidewalls is formed so that the crystal plane of the second layer parallel to the tapered sidewalls is one of the {1-101} crystal planes.

公开(公告)号：US10263069B2

公开(公告)日：2019-04-16

申请号：US15452955

申请日：2017-03-08

Applicant: IMEC VZW

Inventor： Steve Stoffels ,  Yoganand Saripalli

IPC: H01L29/06 ,  H01L21/225 ,  H01L21/285 ,  H01L21/306 ,  H01L21/324 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/861 ,  H01L29/417 ,  H01L29/10 ,  H01L29/423 ,  H01L29/207

Abstract: The present disclosure is related to a III-Nitride semiconductor device comprising a base substrate, a buffer layer, a channel layer, a barrier layer so that a 2-dimensional charge carrier gas is formed or can be formed near the interface between the channel layer and the barrier layer, and at least one set of a first and second electrode in electrical contact with the 2-dimensional charge carrier gas, wherein the device further comprises a mobile charge layer (MCL) within the buffer layer or near the interface between the buffer layer and the channel layer, when the device is in the on-state. The device further comprises an electrically conductive path between one of the electrodes and the mobile charge layer. The present disclosure is also related to a method for producing a device according to the present disclosure.

公开(公告)号：US20190051732A1

公开(公告)日：2019-02-14

申请号：US16050776

申请日：2018-07-31

Applicant: IMEC VZW

Inventor： Steve Stoffels

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/20 ,  H01L29/778 ,  H01L29/47 ,  H01L21/285

CPC classification number: H01L29/66462 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02579 ,  H01L21/28581 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/47 ,  H01L29/7786

Abstract: An enhancement-mode transistor and method for forming a gate of an enhancement-mode transistor are provided. The method includes: (a) providing a p-doped AlxGayInzN gate layer, consisting of a first part and a second part on top of the first part, above a p-doped Alx′Gay′Inz′N channel layer of an enhancement-mode transistor under construction; and (b) providing a metal gate layer on the top surface of the second part, the metal gate layer being formed of a material such as to form a Schottky barrier with the second part, wherein providing the p-doped AlxGayInzN gate layer comprises the steps of: (a1) growing the first part above the p-doped Alx′Gay′Inz′N channel layer of the enhancement-mode transistor under construction, the first part having an average Mg concentration of at most 3×1019 atoms/cm3, and (a2) growing the second part on the first part, the second part having an average Mg concentration higher than 3×1019 atoms/cm3 and having a top surface having a Mg concentration higher than 6×1019 atoms/cm3.

公开(公告)号：US11114537B2

公开(公告)日：2021-09-07

申请号：US16748192

申请日：2020-01-21

Applicant: IMEC VZW

Inventor： Steve Stoffels ,  Niels Posthuma ,  Brice De Jaeger

IPC: H01L29/47 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778 ,  H01L21/285 ,  H01L21/3213

Abstract: Example embodiments relate to enhancement-mode high electron mobility transistors. One embodiment includes a method for manufacturing an enhancement-mode high electron mobility transistor. The method includes providing a stack of layers. The stack of layers includes a substrate, a III-V channel layer over the substrate, a III-V barrier layer on the channel layer, a p-doped III-V layer on the III-V barrier layer, and a Schottky contact interlayer on the p-doped III-V layer. The p-doped III-V layer has a first surface area. The Schottky contact interlayer has a second surface area. The second surface area is less than the first surface area. The second surface area leaves a peripheral part of a top surface of the p-doped III-V layer uncovered. The method also includes depositing a metal gate on the Schottky contact interlayer.

公开(公告)号：US20200235218A1

公开(公告)日：2020-07-23

申请号：US16748192

申请日：2020-01-21

Applicant: IMEC VZW

Inventor： Steve Stoffels ,  Niels Posthuma ,  Brice De Jaeger

IPC: H01L29/47 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L21/3213 ,  H01L21/285 ,  H01L29/66

Abstract: Example embodiments relate to enhancement-mode high electron mobility transistors. One embodiment includes a method for manufacturing an enhancement-mode high electron mobility transistor. The method includes providing a stack of layers. The stack of layers includes a substrate, a III-V channel layer over the substrate, a III-V barrier layer on the channel layer, a p-doped III-V layer on the III-V barrier layer, and a Schottky contact interlayer on the p-doped III-V layer. The p-doped III-V layer has a first surface area. The Schottky contact interlayer has a second surface area. The second surface area is less than the first surface area. The second surface area leaves a peripheral part of a top surface of the p-doped III-V layer uncovered. The method also includes depositing a metal gate on the Schottky contact interlayer.