A pixel clock generating device includes a high-frequency clock generator, a comparer, a pixel clock generator, and a value switcher. The high-frequency clock generator is configured to generate a high-frequency clock. The comparer is configured to measure a time interval between a leading-end synchronizing signal and a trailing-end synchronizing signal in a main scanning and calculate an error between the time interval and a target value. The pixel clock generator is configured to generate a pixel clock based on the high-frequency clock and a pixel clock frequency and correct the pixel clock based on the error. The value switcher, including a plurality of groups of values with which the pixel clock is generated, is configured to switch between the plurality of groups of values according to a switching signal after the trailing-end synchronizing signal is inputted, the comparer calculates the error, and the pixel clock generator corrects the pixel clock.