- 专利标题: Reference clock frequency change handling in a phase-locked loop
-
申请号: US16427826申请日: 2019-05-31
-
公开(公告)号: US10727844B1公开(公告)日: 2020-07-28
- 发明人: Xue-Mei Gong , James D. Barnette , Krishnan Balakrishnan
- 申请人: Silicon Laboratories Inc.
- 申请人地址: US TX Austin
- 专利权人: Silicon Laboratories Inc.
- 当前专利权人: Silicon Laboratories Inc.
- 当前专利权人地址: US TX Austin
- 代理机构: Zagorin Cave LLP
- 主分类号: H03L1/02
- IPC分类号: H03L1/02 ; H03L7/093 ; H03K5/26
摘要:
A method for operating a phase-locked loop includes generating a phase difference signal based on an input clock signal and a feedback clock signal. The method includes filtering a loop filter input signal based on the phase difference signal to generate a loop filter output signal. The feedback clock signal is based on the loop filter output signal. The method includes transitioning a frequency of an output clock signal of the phase-locked loop from a first frequency to a target frequency responsive to detection of a catastrophic cycle slip event in the absence of an out-of-frequency event.
信息查询