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公开(公告)号：US20210409031A1
公开(公告)日：2021-12-30
申请号：US16917828
申请日：2020-06-30
Applicant: Silicon Laboratories Inc.
Inventor： Harihara Subramanian Ranganathan , Xue-Mei Gong , James D. Barnette , Nathan J. Shashoua , Srisai Rao Seethamraju
Abstract: A clock product includes a first phase-locked loop circuit including a first frequency divider. The first phase-locked loop circuit is configured to generate a first clock signal tracking a first reference clock signal and a second reference clock signal. The first phase-locked loop circuit is controlled by a first divide value and a first divide value adjustment based on the first reference clock signal. The clock product includes a circuit including a second frequency divider. The circuit is configured to generate a second clock signal based on the first clock signal, a second divide value, and a second divide value adjustment. The second clock signal tracks the second reference clock signal. The second divide value adjustment is based on the first divide value adjustment and opposes the first divide value adjustment.
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公开(公告)号：US20140118172A1
公开(公告)日：2014-05-01
申请号：US13664902
申请日：2012-10-31
Applicant: SILICON LABORATORIES INC.
Inventor： Xue-Mei Gong , Douglas F. Pastorello
IPC: H03M1/66
CPC classification number: H03M1/0673 , H03M1/0665 , H03M1/74 , H03M3/464 , H03M1/66 , H03M1/46
Abstract: A technique includes selectively enabling a first sequence of unit elements of a plurality of unit elements of a digital-to-analog converter to convert a digital code to a plurality of analog signals in response to a plurality of control signals. Individual control signals of the plurality of control signals and individual analog signals of the plurality of analog signals correspond to respective unit elements of the plurality of unit elements. The technique includes generating the plurality of control signals based on the digital code, a random digital code having a number of bits based on a feedback signal, and an indicator of a second sequence of unit elements of the plurality of unit elements enabled in response to a prior digital code.
Abstract translation: 一种技术包括：响应于多个控制信号，选择性地启用数模转换器的多个单位元件的单元的第一序列将数字代码转换成多个模拟信号。 多个模拟信号中的多个控制信号和各个模拟信号的单独控制信号对应于多个单位元件中的相应单元。 该技术包括基于数字码产生多个控制信号，基于反馈信号具有多个位的随机数字码，以及响应于所述多个单元的单元的第二序列的指示符 以前的数字代码。
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公开(公告)号：US10951216B1
公开(公告)日：2021-03-16
申请号：US16600793
申请日：2019-10-14
Applicant: Silicon Laboratories Inc.
Inventor： James D. Barnette , William Anker , Xue-Mei Gong
Abstract: A method includes generating a filtered phase difference signal based on a reference clock signal and a feedback clock signal. The method includes generating a first output clock signal based on a first divider control signal and an input clock signal. The feedback clock signal is based on the first output clock signal. The method includes generating a first time code based on a counter signal and a first update of the first output clock signal in response to an update of the filtered phase difference signal to a first value from a second value. The second output clock signal is based on a second divider control signal, the input clock signal, and an error correction signal generated based on the first value, the second value, the first time code, and the second time code. The first and second divider control signals are based on the filtered phase difference signal.
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公开(公告)号：US08736476B2
公开(公告)日：2014-05-27
申请号：US13664902
申请日：2012-10-31
Applicant: Silicon Laboratories Inc.
Inventor： Xue-Mei Gong , Douglas F. Patorello
CPC classification number: H03M1/0673 , H03M1/0665 , H03M1/74 , H03M3/464 , H03M1/66 , H03M1/46
Abstract: A technique includes selectively enabling a first sequence of unit elements of a plurality of unit elements of a digital-to-analog converter to convert a digital code to a plurality of analog signals in response to a plurality of control signals. Individual control signals of the plurality of control signals and individual analog signals of the plurality of analog signals correspond to respective unit elements of the plurality of unit elements. The technique includes generating the plurality of control signals based on the digital code, a random digital code having a number of bits based on a feedback signal, and an indicator of a second sequence of unit elements of the plurality of unit elements enabled in response to a prior digital code.
Abstract translation: 一种技术包括：响应于多个控制信号，选择性地启用数模转换器的多个单位元件的单元的第一序列将数字代码转换成多个模拟信号。 多个模拟信号中的多个控制信号和各个模拟信号的单独控制信号对应于多个单位元件中的相应单元。 该技术包括基于数字码产生多个控制信号，基于反馈信号具有多个位的随机数字码，以及响应于所述多个单元的单元的第二序列的指示符 以前的数字代码。
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公开(公告)号：US10826507B1
公开(公告)日：2020-11-03
申请号：US16404056
申请日：2019-05-06
Applicant: Silicon Laboratories Inc.
Inventor： Xue-Mei Gong , James D. Barnette
Abstract: A clock product includes a phase-locked loop configured to generate an output clock signal based on an input digital value and a feedback digital value. The input digital value corresponds to a first clock edge of a frequency-divided input clock signal and the feedback digital value corresponds to a second clock edge of a feedback clock signal. The clock product includes an input fractional divider configured to generate the input digital value based on an input clock signal, a divider value, and an input clock period digital code corresponding to a period of the input clock signal.
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Patent Agency Ranking
公开(公告)号：US20210184687A1
公开(公告)日：2021-06-17
申请号：US17186180
申请日：2021-02-26
Applicant: Silicon Laboratories Inc.
Inventor： James D. Barnette , William Anker , Xue-Mei Gong
Abstract: A method for operating a clock product includes selectively coupling a first output divider and a second output divider based on a determination of whether the first divider value is integrally related to the second divider value. In response to the first divider value being integrally related to the second divider value, the selectively coupling includes cascading the first output divider with the second output divider. In in response to the first divider value being non-integrally related to the second divider value, the selectively coupling includes configuring the second output divider to be cascaded with a first phase-locked loop and in parallel with the first output divider and to be responsive to an error correction signal based on a difference in response times of the first output divider and the second output divider to a change in a filtered phase difference signal of the first phase-locked loop.
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公开(公告)号：US10727844B1
公开(公告)日：2020-07-28
申请号：US16427826
申请日：2019-05-31
Applicant: Silicon Laboratories Inc.
Inventor： Xue-Mei Gong , James D. Barnette , Krishnan Balakrishnan
Abstract: A method for operating a phase-locked loop includes generating a phase difference signal based on an input clock signal and a feedback clock signal. The method includes filtering a loop filter input signal based on the phase difference signal to generate a loop filter output signal. The feedback clock signal is based on the loop filter output signal. The method includes transitioning a frequency of an output clock signal of the phase-locked loop from a first frequency to a target frequency responsive to detection of a catastrophic cycle slip event in the absence of an out-of-frequency event.
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公开(公告)号：US10693475B1
公开(公告)日：2020-06-23
申请号：US16427837
申请日：2019-05-31
Applicant: Silicon Laboratories Inc.
Inventor： Xue-Mei Gong , James D. Barnette
IPC: H03L7/093
Abstract: A method for generating a clock signal by a phase-locked loop includes generating a phase difference signal based on an input clock signal and a feedback clock signal and generating a loop filter output signal. In a first mode, the loop filter output signal is generated based on the phase difference signal and a predetermined frequency slope, and may include generating a phase-slope-limited version of the phase difference signal based on a predetermined phase slope limit and generating a frequency-slope-limited version of the phase difference signal based on the predetermined frequency slope limit. In a second mode, the loop filter output signal may be generated based on the predetermined frequency slope limit, a value of the loop filter output signal, and a target frequency. In the second mode, the loop filter output signal may be generated further based on a predetermined frequency step value.
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公开(公告)号：US11342926B2
公开(公告)日：2022-05-24
申请号：US17186180
申请日：2021-02-26
Applicant: Silicon Laboratories Inc.
Inventor： James D. Barnette , William Anker , Xue-Mei Gong
Abstract: A method for operating a clock product includes selectively coupling a first output divider and a second output divider based on a determination of whether the first divider value is integrally related to the second divider value. In response to the first divider value being integrally related to the second divider value, the selectively coupling includes cascading the first output divider with the second output divider. In in response to the first divider value being non-integrally related to the second divider value, the selectively coupling includes configuring the second output divider to be cascaded with a first phase-locked loop and in parallel with the first output divider and to be responsive to an error correction signal based on a difference in response times of the first output divider and the second output divider to a change in a filtered phase difference signal of the first phase-locked loop.
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公开(公告)号：US11245406B2
公开(公告)日：2022-02-08
申请号：US16917828
申请日：2020-06-30
Applicant: Silicon Laboratories Inc.
Inventor： Harihara Subramanian Ranganathan , Xue-Mei Gong , James D. Barnette , Nathan J. Shashoua , Srisai Rao Seethamraju
Abstract: A clock product includes a first phase-locked loop circuit including a first frequency divider. The first phase-locked loop circuit is configured to generate a first clock signal tracking a first reference clock signal and a second reference clock signal. The first phase-locked loop circuit is controlled by a first divide value and a first divide value adjustment based on the first reference clock signal. The clock product includes a circuit including a second frequency divider. The circuit is configured to generate a second clock signal based on the first clock signal, a second divide value, and a second divide value adjustment. The second clock signal tracks the second reference clock signal. The second divide value adjustment is based on the first divide value adjustment and opposes the first divide value adjustment.
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