Invention Grant
- Patent Title: Progressive length error control code
-
Application No.: US16105663Application Date: 2018-08-20
-
Publication No.: US10733050B2Publication Date: 2020-08-04
- Inventor: J. Thomas Pawlowski
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Fletcher Yoder, P.C.
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G06F11/10 ; G06F3/06

Abstract:
Devices and methods may be used to append a scalable (1) of parity bits in a data packet that scales with a number of data bits in a payload of the data packet. The parity bits may be generated utilizing a table of entries. In some examples, each entry in the table corresponds to a number of the data bits to be included in the payload; and each column of the table may be used to generate a corresponding parity bit of the one or more parity bits.
Public/Granted literature
- US20190361776A1 PROGRESSIVE LENGTH ERROR CONTROL CODE Public/Granted day:2019-11-28
Information query