公开(公告)号：US12067767B2

公开(公告)日：2024-08-20

申请号：US17332369

申请日：2021-05-27

Applicant: Micron Technology, Inc.

Inventor： J. Thomas Pawlowski

IPC: G06V10/94

CPC classification number: G06V10/955 ,  G06F2207/025 ,  G06F2218/00

Abstract: Disclosed are methods and systems, among which is a system that includes a pattern-recognition processor, a central processing unit (CPU) coupled to the pattern-recognition processor via a pattern-recognition bus, and memory coupled to the CPU via a memory bus. In some embodiments, the pattern-recognition bus and the memory bus form about the same number of connections to the pattern-recognition processor and the memory, respectively.

公开(公告)号：US11625321B2

公开(公告)日：2023-04-11

申请号：US17079138

申请日：2020-10-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David A. Roberts ,  J. Thomas Pawlowski ,  Robert Walker

IPC: G06F12/02 ,  G06F13/16

Abstract: Apparatuses and methods for adaptive control of memory are disclosed. One example apparatus includes a memory translation unit configured to receive a memory access request including a requested address and to determine a mapping state of a region of a memory associated with the requested address. The memory translation unit further configured to provide a mapped address to the memory. The mapped address is selected from one of the requested address or a translated requested address based on the state of the region of the memory associated with the requested address.

公开(公告)号：US11194480B2

公开(公告)日：2021-12-07

申请号：US16696667

申请日：2019-11-26

Applicant: Micron Technology, Inc.

Inventor： J. Thomas Pawlowski

IPC: G06F11/00 ,  G06F3/06 ,  G06F13/16 ,  G06F11/10 ,  G06F13/38 ,  G06F11/07 ,  G11C29/52 ,  H04L1/18 ,  H04L12/801 ,  H04L12/825 ,  H04L12/873

Abstract: A memory device includes a memory component that stores data and a processor. The processor may receive requests from a requesting component to perform a plurality of data operations, generate a plurality of packets associated with the plurality of data operations, and continuously transmit each of the plurality of packets until each of the plurality of packets are transmitted. Each of the plurality of packets after the first packet of the plurality of packets is transmitted on a subsequent clock cycle immediately after a previous packet is transmitted.

公开(公告)号：US10733050B2

公开(公告)日：2020-08-04

申请号：US16105663

申请日：2018-08-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： J. Thomas Pawlowski

IPC: G11C29/00 ,  G06F11/10 ,  G06F3/06

Abstract: Devices and methods may be used to append a scalable (1) of parity bits in a data packet that scales with a number of data bits in a payload of the data packet. The parity bits may be generated utilizing a table of entries. In some examples, each entry in the table corresponds to a number of the data bits to be included in the payload; and each column of the table may be used to generate a corresponding parity bit of the one or more parity bits.

公开(公告)号：US20200097191A1

公开(公告)日：2020-03-26

申请号：US16696667

申请日：2019-11-26

Applicant: Micron Technology, Inc.

Inventor： J. Thomas Pawlowski

IPC: G06F3/06 ,  G06F11/07 ,  H04L12/873 ,  H04L12/825 ,  H04L12/801 ,  H04L1/18 ,  G11C29/52 ,  G06F11/10 ,  G06F13/38 ,  G06F13/16

Abstract: A memory device includes a memory component that stores data and a processor. The processor may receive requests from a requesting component to perform a plurality of data operations, generate a plurality of packets associated with the plurality of data operations, and continuously transmit each of the plurality of packets until each of the plurality of packets are transmitted. Each of the plurality of packets after the first packet of the plurality of packets is transmitted on a subsequent clock cycle immediately after a previous packet is transmitted.

公开(公告)号：US10572164B2

公开(公告)日：2020-02-25

申请号：US15637327

申请日：2017-06-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： J. Thomas Pawlowski

IPC: G06F3/06 ,  G06F13/16 ,  G06F11/10 ,  G06F13/38 ,  G06F11/07 ,  G11C29/52 ,  H04L1/18 ,  H04L12/801 ,  H04L12/825 ,  H04L12/873

Abstract: A memory device includes a memory component that stores data. The memory device also includes a processor that receives a signal indicating that the memory component is coupled to the processor and retrieves information from the memory component. The information may include one or more algorithms capable of being performed by the memory component. The processor may then receive one or more packets associated with one or more data operations regarding the memory component. The processor may then perform the one or more data operations by using the memory component to employ the one or more algorithms.

公开(公告)号：US10540104B2

公开(公告)日：2020-01-21

申请号：US15666410

申请日：2017-08-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： J. Thomas Pawlowski

IPC: G06F11/00 ,  G06F3/06 ,  G06F13/16 ,  G06F11/10 ,  G06F13/38 ,  G06F11/07 ,  G11C29/52 ,  H04L1/18 ,  H04L12/801 ,  H04L12/825 ,  H04L12/873

Abstract: A memory device includes a memory component that stores data and a processor. The processor may receive requests from a requesting component to perform a plurality of data operations, generate a plurality of packets associated with the plurality of data operations, and continuously transmit each of the plurality of packets until each of the plurality of packets are transmitted. Each of the plurality of packets after the first packet of the plurality of packets is transmitted on a subsequent clock cycle immediately after a previous packet is transmitted.

公开(公告)号：US20190361776A1

公开(公告)日：2019-11-28

申请号：US16105663

申请日：2018-08-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： J. Thomas Pawlowski

IPC: G06F11/10 ,  G06F3/06

Abstract: Devices and methods may be used to append a scalable (1) of parity bits in a data packet that scales with a number of data bits in a payload of the data packet. The parity bits may be generated utilizing a table of entries. In some examples, each entry in the table corresponds to a number of the data bits to be included in the payload; and each column of the table may be used to generate a corresponding parity bit of the one or more parity bits.

公开(公告)号：US20190102095A1

公开(公告)日：2019-04-04

申请号：US16208035

申请日：2018-12-03

Applicant: Micron Technology, Inc.

Inventor： J. Thomas Pawlowski

IPC: G06F3/06 ,  G06F13/38 ,  G06F11/07 ,  G06F11/10 ,  G06F13/16 ,  H04L12/801 ,  H04L12/825 ,  H04L12/873 ,  H04L1/18 ,  G11C29/52

Abstract: A memory device includes a memory component that stores data and a processor. The processor may receive requests from a requesting component to perform a plurality of data operations, generate a plurality of packets associated with the plurality of data operations, and continuously transmit each of the plurality of packets until each of the plurality of packets are transmitted. Each of the plurality of packets after the first packet of the plurality of packets is transmitted on a subsequent clock cycle immediately after a previous packet is transmitted.

公开(公告)号：US20170300382A1

公开(公告)日：2017-10-19

申请号：US15637327

申请日：2017-06-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： J. Thomas Pawlowski

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

Abstract: A memory device includes a memory component that stores data. The memory device also includes a processor that receives a signal indicating that the memory component is coupled to the processor and retrieves information from the memory component. The information may include one or more algorithms capable of being performed by the memory component. The processor may then receive one or more packets associated with one or more data operations regarding the memory component. The processor may then perform the one or more data operations by using the memory component to employ the one or more algorithms.