Invention Grant
- Patent Title: Boundary protection for CMOS multi-threshold voltage devices
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Application No.: US16059319Application Date: 2018-08-09
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Publication No.: US10741454B2Publication Date: 2020-08-11
- Inventor: Jing Guo , Ekmini A. De Silva , Nicolas Loubet , Indira Seshadri , Nelson Felix
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Vazken Alexanian
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L21/8234 ; H01L21/768 ; H01L27/108

Abstract:
Methods are presented for forming multi-threshold field effect transistors. The methods generally include depositing and patterning an organic planarizing layer to protect underlying structures formed in a selected one of the nFET region and the pFET region of a semiconductor wafer. In the other one of the nFET region and the pFET region, structures are processed to form an undercut in the organic planarizing layer. The organic planarizing layer is subjected to a reflow process to fill the undercut. The methods are effective to protect a boundary between the nFET region and the pFET region.
Public/Granted literature
- US20200051872A1 BOUNDARY PROTECTION FOR CMOS MULTI-THRESHOLD VOLTAGE DEVICES Public/Granted day:2020-02-13
Information query
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