A semiconductor device including a substrate having a fin structure surrounded by a trench isolation region; a trench disposed in the fin structure; an interlayer dielectric layer disposed on the substrate; a working gate striding over the fin structure and on the first side of the trench; a dummy gate striding over the fin structure and on the second side of the trench; a doped source region in the fin structure; and a doped drain region in the fin structure. The dummy gate is disposed between the trench and the doped drain region. The fin structure extends along a first direction and the dummy gate extends along a second direction. The first direction is not parallel with the second direction.