Invention Grant
- Patent Title: Semiconductor device including buried insulation layer and manufacturing method thereof
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Application No.: US15928105Application Date: 2018-03-22
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Publication No.: US10763170B2Publication Date: 2020-09-01
- Inventor: Purakh Raj Verma , Su Xing , Ching-Yang Wen
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Hsin-Chu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@2a82155c
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L27/12 ; H01L23/48 ; H01L23/528 ; H01L29/786 ; H01L29/417 ; H01L23/522 ; H01L21/84

Abstract:
A semiconductor device includes a buried insulation layer, a semiconductor layer, a gate structure, a source doped region, and a drain doped region. The semiconductor layer is disposed on the buried insulation layer. The gate structure is disposed on the semiconductor layer. The semiconductor layer includes a body region disposed between the gate structure and the buried insulation layer. The source doped region and the drain doped region are disposed in the semiconductor layer. A first contact structure penetrates the buried insulation layer and contacts the body region. A second contact structure penetrates the buried insulation layer and is electrically connected with the source doped region. At least a part of the first contact structure overlaps the body region in a thickness direction of the buried insulation layer. The body region is electrically connected with the source doped region via the first contact structure and the second contact structure.
Public/Granted literature
- US20190252253A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Public/Granted day:2019-08-15
Information query
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