Invention Grant
- Patent Title: Nano-wire resistance model
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Application No.: US15823252Application Date: 2017-11-27
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Publication No.: US10776552B2Publication Date: 2020-09-15
- Inventor: Victor Moroz , Ibrahim Avci , Shuqing Li , Philippe Roussel , Ivan Ciofi
- Applicant: Synopsys, Inc.
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Haynes Beffel & Wolfeld LLP
- Agent Warren S. Wolfeld; Andrew L. Dunlap
- Main IPC: G06F30/394
- IPC: G06F30/394 ; G06F30/33 ; G06F30/327 ; G06F30/367 ; G06F30/398 ; G06F30/3312 ; H01L29/06 ; H01L23/50 ; G06F111/10

Abstract:
An integrated circuit design tool for modeling resistance of an interconnect specifies a structure of the interconnect in a data structure in memory in or accessible by the computer system using 3D coordinate system. For each of a plurality of volume elements in the specified structure, the tool specifies a location and one of first and second materials of the interconnect having specified resistivities, and for each volume element generates a model resistivity for the volume element as a function of resistivity of volume elements within a neighborhood of the volume element and a specified transition region length λ.
Public/Granted literature
- US20180157783A1 NANO-WIRE RESISTANCE MODEL Public/Granted day:2018-06-07
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