公开(公告)号：US20240354477A1

公开(公告)日：2024-10-24

申请号：US18137382

申请日：2023-04-20

申请人： Synopsys, Inc.

发明人： Navneet KAKKAR ,  Sridhar KELADI

IPC分类号： G06F30/327 ,  G06F30/33

CPC分类号： G06F30/327 ,  G06F30/33

摘要： Certain aspects are directed to apparatus and methods for logic synthesis. One example method generally includes: receiving a logic design including a representation of a plurality of registers and ports; detecting one or more constant, equal, or opposite registers or ports of the plurality of registers and ports by analyzing logic across a hierarchy boundary identified for the logic synthesis; and generating a netlist by modifying the logic based on the detection.

公开(公告)号：US12125787B2

公开(公告)日：2024-10-22

申请号：US17037569

申请日：2020-09-29

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jae-Boong Lee ,  Jung-Ho Do ,  Tae-Joong Song ,  Seung-Young Lee ,  Jong-Hoon Jung ,  Ji-Su Yu

IPC分类号： H01L23/528 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L27/118 ,  G06F115/02

CPC分类号： H01L23/5286 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/11807 ,  G06F2115/02 ,  H01L27/088 ,  H01L27/092 ,  H01L2027/11881

摘要： An integrated circuit including: a power rail including first and second conductive lines spaced apart from each other in a vertical direction, wherein the first and second conductive lines extend in parallel to each other in a first horizontal direction, and are electrically connected to each other, to supply power to a first standard cell, wherein the first and second conductive lines are disposed at a boundary of the first standard cell; and a third conductive line between the first and second conductive lines and extending in a second horizontal direction orthogonal to the first horizontal direction, to transfer an input signal or an output signal of the first standard cell.

公开(公告)号：US20240346217A1

公开(公告)日：2024-10-17

申请号：US18299427

申请日：2023-04-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jaw-Juinn Horng ,  Szu-Chin Tsao

IPC分类号： G06F30/33 ,  G06F30/327

CPC分类号： G06F30/33 ,  G06F30/327

摘要： An integrated circuit includes a core domain having at least one core domain design rule limitation of a smaller device and a lower operating voltage, an input/output domain having at least one input/output domain design rule limitation of a larger device than the smaller device of the core domain and a higher operating voltage than the lower operating voltage of the core domain, and a mapping cell that includes two or more electrical devices that each meet the at least one core domain design rule limitation. The mapping cell is configured to be an input/output device and operate in the input/output domain at the higher operating voltage of the input/output domain.

公开(公告)号：US12093619B2

公开(公告)日：2024-09-17

申请号：US18314029

申请日：2023-05-08

申请人： Celera, Inc.

发明人： Calum MacRae ,  John Mason ,  Karen Mason

IPC分类号： G06F30/327 ,  G06F30/31 ,  G06F30/347 ,  G06F30/367 ,  G06F30/373 ,  G06F30/38 ,  G06F30/392 ,  G06F30/398 ,  G06F111/12

CPC分类号： G06F30/327 ,  G06F30/31 ,  G06F30/347 ,  G06F30/367 ,  G06F30/38 ,  G06F30/392 ,  G06F30/398 ,  G06F30/373 ,  G06F2111/12

摘要： In some embodiments, information specifying a transistor to be generated is received, the information comprising an on resistance. A total width of a gate of the transistor to be generated is determined based at least on the on resistance. A first width, a number of fingers (F), and a number of device cells (P) are determined based on the total width. A transistor level schematic is generated comprising one or more transistors configured with the first width and the number of fingers (F). A layout is generated, wherein the layout comprises P device cells, each device cell comprising a plurality of gates corresponding to said number of fingers (F) each gate having said first width, wherein the device cells are configured in a two-dimensional array.

公开(公告)号：US12073308B2

公开(公告)日：2024-08-27

申请号：US15423279

申请日：2017-02-02

申请人： STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

发明人： Thomas Boesch ,  Giuseppe Desoli

IPC分类号： G06N3/063 ,  G06F30/327 ,  G06F30/34 ,  G06F30/347 ,  G06N3/044 ,  G06N3/045 ,  G06N3/0464 ,  G06N3/047 ,  G06N3/084 ,  G06N20/00 ,  G06N20/10 ,  G06F9/445 ,  G06F13/40 ,  G06F15/78 ,  G06F115/02 ,  G06F115/08 ,  G06N3/04 ,  G06N3/08 ,  G06N7/01

CPC分类号： G06N3/0464 ,  G06F30/327 ,  G06F30/34 ,  G06F30/347 ,  G06N3/044 ,  G06N3/045 ,  G06N3/047 ,  G06N3/084 ,  G06N20/00 ,  G06N20/10 ,  G06F9/44505 ,  G06F13/4022 ,  G06F15/7817 ,  G06F2115/02 ,  G06F2115/08 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06N7/01

摘要： Embodiments are directed towards a hardware accelerator engine that supports efficient mapping of convolutional stages of deep neural network algorithms. The hardware accelerator engine includes a plurality of convolution accelerators, and each one of the plurality of convolution accelerators includes a kernel buffer, a feature line buffer, and a plurality of multiply-accumulate (MAC) units. The MAC units are arranged to multiply and accumulate data received from both the kernel buffer and the feature line buffer. The hardware accelerator engine also includes at least one input bus coupled to an output bus port of a stream switch, at least one output bus coupled to an input bus port of the stream switch, or at least one input bus and at least one output bus hard wired to respective output bus and input bus ports of the stream switch.

公开(公告)号：US20240256747A1

公开(公告)日：2024-08-01

申请号：US18565473

申请日：2021-10-27

申请人： SHANGHAI GUOWEI SILCORE TECHNOLOGY CO., LTD.

发明人： Zhongwei Shao ,  Jifeng Zhang

IPC分类号： G06F30/327 ,  G06F8/41

CPC分类号： G06F30/327 ,  G06F8/427

摘要： Embodiments of the present description provide a statement block encapsulation method and apparatus, an electronic device, and a storage medium, being applied to the technical field of electronic design automation. The encapsulation method comprises: according to a segmentation boundary obtained by an RTL segmentation tool, determining a plurality of statement blocks to be encapsulated; traversing each statement block to be encapsulated, wherein a module where the current statement block to be encapsulated is located is used as the current processing module; and scanning the current processing module, determining whether the current processing module comprises a black box signal, and according to the black box signal, clustering a sub-module and the statement block to perform encapsulation processing. The black box signal is used as a bond to perform encapsulation processing, so that the RTL segmentation tool is suitable for performing encapsulation processing on the sub-modules and the statement blocks under different syntax rules, improving the processing efficiency, and achieving fast layout planning.

公开(公告)号：US12050853B2

公开(公告)日：2024-07-30

申请号：US18225020

申请日：2023-07-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chao Tong ,  Qingwen Deng

IPC分类号： G06F30/398 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  G06N7/02

CPC分类号： G06F30/398 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  G06N7/023

摘要： Systems and methods include receiving a functional integrated circuit design and generating a plurality of place and route (PnR) layouts based on the received functional integrated circuit design and one or more integrated circuit floorplans may be generated. One or more fuzzy logic rules may be applied to analyze attributes associated with each of the generated PnR layouts, and a PnR layout of the plurality of PnR layouts having an area utilization complying with the one or more fuzzy logic rules may be generated.

公开(公告)号：US12026444B2

公开(公告)日：2024-07-02

申请号：US17522834

申请日：2021-11-09

申请人： Xilinx, Inc.

发明人： Hao Yu ,  Jun Liu

IPC分类号： G06F30/343 ,  G06F30/327 ,  G06F30/347

CPC分类号： G06F30/343 ,  G06F30/327 ,  G06F30/347

摘要： Dynamic port handling for circuit designs can include inserting, within a static isolated module of a circuit design, static drivers configured to drive isolated modules of reconfigurable module (RM) instances for inclusion in an RM of the circuit design. For each RM instance of a plurality of RM instances to be inserted into the RM, one or more additional ports can be inserted in the RM based on a number of isolated modules included in a current RM instance. Further, net(s) corresponding to the additional port(s) can be created. The circuit design, including the current RM instance, the additional port(s), and the net(s), can be placed and routed. Prior to the inserting and the performing place and route for a next RM instance to be inserted into the RM, the current RM instance can be removed from the RM along with the additional port(s) and the net(s).

公开(公告)号：US20240193339A1

公开(公告)日：2024-06-13

申请号：US18532496

申请日：2023-12-07

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jordan Timothy Davis ,  Woojin Seo ,  Chanhee Jeon

IPC分类号： G06F30/392 ,  G06F30/327 ,  G06F30/394

CPC分类号： G06F30/392 ,  G06F30/327 ,  G06F30/394 ,  G06F2115/06

摘要： In an example method of analyzing an electrostatic discharge (ESD) network, input data characterizing a semiconductor device is received. The semiconductor device includes an input/output (I/O) pad, an ESD protection circuit, and at least one functional circuit. A common resistance of the ESD protection circuit is calculated based on the input data and using a plurality of resistances and at least one predetermined equation. The plurality of resistances are associated with the I/O pad, the ESD protection circuit, and the at least one functional circuit. A network analysis is performed on the semiconductor device by excluding the common resistance.

公开(公告)号：US12001773B2

公开(公告)日：2024-06-04

申请号：US18295085

申请日：2023-04-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shin-Chi Chen ,  King-Ho Tam ,  Yu-Ze Lin ,  Huang-Yu Chen

IPC分类号： G06F30/30 ,  G06F30/31 ,  G06F30/327 ,  G06F30/392 ,  G06F119/18

CPC分类号： G06F30/392 ,  G06F30/31 ,  G06F30/327 ,  G06F2119/18

摘要： A method in certain embodiments includes using a computer system that includes an EDA tool to generate a layout of an IC device; searching, using a statistical method such as Bayesian optimization process, for one or more input variable parameters, such as the dimensions of the IC device and the dimensions of the voltage areas in the IC device, that results in an optimal characteristic, such as power, performance or area (PPA) of the IC device, subject to a limiting condition, such as one determined using a cost function. A computer system including one or more EDAs configured to perform the method is also disclosed.