Invention Grant
- Patent Title: Semiconductor device including a pad and a wiring line arranged for bringing a probe into contact with the pad and method of manufacturing the same
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Application No.: US15774664Application Date: 2016-02-23
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Publication No.: US10777507B2Publication Date: 2020-09-15
- Inventor: Yoshinori Deguchi , Akinobu Watanabe
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Tokyo
- Agency: SGPatents PLLC
- International Application: PCT/JP2016/055198 WO 20160223
- International Announcement: WO2017/145256 WO 20170831
- Main IPC: H01L23/535
- IPC: H01L23/535 ; H01L21/3205 ; H01L23/522 ; H01L21/768 ; H01L21/66 ; H01L23/538 ; H01L23/00 ; H01L23/58
Abstract:
A semiconductor device having a plurality of wiring layers including a first wiring layer and a second wiring layer, with the first wiring layer being the uppermost layer and including a pad PD that has a first region for bonding a copper wire, and a second region for bringing a probe into contact with the pad. The second wiring layer is one layer below the first wiring layer and includes a first wiring line arranged immediately below the second region of the pad, the second wiring layer having no conductor pattern at a region overlapping with the first region of the pad PD.
Public/Granted literature
- US20180374795A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2018-12-27
Information query
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