Invention Grant
- Patent Title: Standard cell architecture for gate tie-off
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Application No.: US16781820Application Date: 2020-02-04
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Publication No.: US10777640B2Publication Date: 2020-09-15
- Inventor: Xiangdong Chen , Venugopal Boynapalli , Hyeokjin Lim
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: QUALCOMM Incorporated
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L23/532 ; H01L23/522 ; H01L29/66 ; H01L23/528 ; H01L27/118 ; H01L27/02

Abstract:
In certain aspects of the disclosure, a cell includes a first dummy gate extended along a second lateral direction and on a boundary of the cell, a second dummy gate extended along the second lateral direction and on an opposite boundary of the cell, and a third gate extended along the second lateral direction, wherein the third gate is between the first dummy gate and the second dummy gate. The cell also includes a source between the second dummy gate and the third gate electrically coupled to a power rail. The cell further includes a metal interconnect extended along a first lateral direction approximately perpendicular to the second lateral direction and above the first dummy gate, the source, and the third gate, wherein the metal interconnect is configured to couple the first dummy gate to the power rail through the source.
Public/Granted literature
- US20200176562A1 NOVEL STANDARD CELL ARCHITECTURE FOR GATE TIE-OFF Public/Granted day:2020-06-04
Information query
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