Invention Grant
- Patent Title: Integrated circuit chip with strained NMOS and PMOS transistors
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Application No.: US16534557Application Date: 2019-08-07
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Publication No.: US10777680B2Publication Date: 2020-09-15
- Inventor: Remy Berthelon , Francois Andrieu
- Applicant: STMicroelectronics (Crolles 2) SAS , Commissariat A L'Energie Atomique et aux Energies Alternatives
- Applicant Address: FR Crolles FR Paris
- Assignee: STMicroelectronics (Crolles 2) SAS,Commissariat A L'Energie Atomique et aux Energies Alternatives
- Current Assignee: STMicroelectronics (Crolles 2) SAS,Commissariat A L'Energie Atomique et aux Energies Alternatives
- Current Assignee Address: FR Crolles FR Paris
- Agency: Crowe & Dunlevy
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@7d50d1b9
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/8238 ; H01L21/84 ; H01L27/12 ; H01L21/762 ; H01L27/02 ; H01L29/786 ; H01L27/092
Abstract:
Longitudinal trenches extend between and on either side of first and second side-by-side strip areas. Transverse trenches extend from one edge to another edge of the first strip area to define tensilely strained semiconductor slabs in the first strip area, with the second strip area including portions that are compressively strained in the longitudinal direction and/or tensilely strained in the transverse direction. In the first strip area, N-channel MOS transistors are located inside and on top of the semiconductor slabs. In the second strip area, P-channel MOS transistors are located inside and on top of the portions.
Public/Granted literature
- US20190363190A1 INTEGRATED CIRCUIT CHIP WITH STRAINED NMOS AND PMOS TRANSISTORS Public/Granted day:2019-11-28
Information query
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