Invention Grant
- Patent Title: Built-in self-test (BIST) circuit, memory device including the same, and method of operating the BIST circuit
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Application No.: US16274396Application Date: 2019-02-13
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Publication No.: US10783979B2Publication Date: 2020-09-22
- Inventor: Seung-ho Ok , Pyung-moon Zhang , Sang-hoon Shin , Ki-hyun Park , Yong-sik Park
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do
- Agency: Muir Patent Law, PLLC
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@51fc8d89
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G11C29/38 ; G11C29/36 ; G11C29/50

Abstract:
A built-in self-test (BIST) circuit and a method of operating BIST circuit is disclosed. The BIST circuit is configured to generate a test pattern based on a plurality of test parameters including a first test parameter and a second test parameter and perform a test on at least one memory core. The method includes setting a sweep range comprising a sweep start point of the first test parameter and a sweep end point thereof; generating a first test pattern corresponding to each sweep point of the sweep range from the sweep start point of the first test parameter and the sweep end point thereof and providing the first test pattern to the at least one memory core; receiving output data corresponding to the first test pattern from the at least one memory core and comparing the output data and a predetermined reference data; and generating first test result information based on results of the comparing.
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