Invention Grant
- Patent Title: Bonding of laminates with electrical interconnects
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Application No.: US16361116Application Date: 2019-03-21
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Publication No.: US10790222B2Publication Date: 2020-09-29
- Inventor: Javier A. Delacruz , Belgacem Haba , Wael Zohni , Liang Wang , Akash Agrawal
- Applicant: Invensas Corporation
- Applicant Address: US CA San Jose
- Assignee: Invensas Corporation
- Current Assignee: Invensas Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L23/498 ; H01L23/00
Abstract:
A microelectronic assembly including first and second laminated microelectronic elements is provided. A patterned bonding layer is disposed on a face of each of the first and second laminated microelectronic elements. The patterned bonding layers are mechanically and electrically bonded to form the microelectronic assembly.
Public/Granted literature
- US20190221510A1 BONDING OF LAMINATES WITH ELECTRICAL INTERCONNECTS Public/Granted day:2019-07-18
Information query
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