Invention Grant
- Patent Title: Auto zero offset current mitigation at an integrator input
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Application No.: US16184778Application Date: 2018-11-08
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Publication No.: US10790791B2Publication Date: 2020-09-29
- Inventor: Supriya Raveendra Hegde , Hugo Gicquel
- Applicant: STMICROELECTRONICS ASIA PACIFIC PTE LTD
- Applicant Address: SG Singapore
- Assignee: STMicroelectronics Asia Pacific PTE Ltd
- Current Assignee: STMicroelectronics Asia Pacific PTE Ltd
- Current Assignee Address: SG Singapore
- Agency: Seed IP Law Group LLP
- Main IPC: H03F1/02
- IPC: H03F1/02 ; H03F3/45

Abstract:
A feedback stage for an integrator circuit is provided. The integrator receives a first input current and a second input current that include respective measurement current components and an offset current component. The integrator integrates the first input current and the second input current and generates a first output voltage and a second output voltage. The feedback stage including a transconductance amplifier detects a difference between the first output voltage and the second output voltage and sinks or sources a first output current and a second output current based on the difference between the first output voltage and the second output voltage. The first output current is additively combined with the first input current and the second output current is additively combined with the second input current to mitigate the offset current component at an input of the integrator.
Public/Granted literature
- US20200153399A1 AUTO ZERO OFFSET CURRENT MITIGATION AT AN INTEGRATOR INPUT Public/Granted day:2020-05-14
Information query
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