Invention Grant
- Patent Title: Jitter elimination and latency compensation at DetNet transport egress
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Application No.: US16136947Application Date: 2018-09-20
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Publication No.: US10798012B2Publication Date: 2020-10-06
- Inventor: Pascal Thubert , Patrick Wetterwald , Eric Michel Levy-Abegnoli , Jean-Philippe Vasseur
- Applicant: Cisco Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: CISCO TECHNOLOGY, INC.
- Current Assignee: CISCO TECHNOLOGY, INC.
- Current Assignee Address: US CA San Jose
- Agent Leon R. Turkevich
- Main IPC: H04L12/841
- IPC: H04L12/841 ; H04L12/801 ; H04L12/851 ; H04L12/875 ; H04L12/861 ; H04L12/727

Abstract:
In one embodiment, a method comprises receiving, by a transport layer executed by a processor circuit in an apparatus, an identifiable grouping of data; storing, by the transport layer, the data as transport layer packets in a buffer circuit in the apparatus, the storing including inserting into each transport layer packet a grouping identifier that identifies the transport layer packets as belonging to the identifiable grouping; and causing, by the transport layer, a plurality of transmitting deterministic network interface circuits to deterministically retrieve the transport layer packets from the buffer circuit for deterministic transmission across respective deterministic links, the grouping identifier enabling receiving deterministic network interface circuits to group the received transport layer packets, regardless of deterministic link, into a single processing group for a next receiving transport layer.
Public/Granted literature
- US20190132253A1 JITTER ELIMINATION AND LATENCY COMPENSATION AT DETNET TRANSPORT EGRESS Public/Granted day:2019-05-02
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