Reduced quiescent current PVT compensated oscillator
Abstract:
A device includes a capacitor having a first terminal coupled to a ground node, and a second terminal; a first transistor having a source coupled to the capacitor, a drain coupled to a first node, and a gate; a first current source coupled to the first node and configured to couple to a regulated supply node; a second transistor having a source coupled to the ground node, a drain coupled to a second node, and a gate coupled to the second node and to the gate of the first transistor; and a comparator circuit having an input coupled to the first node and an output configured to couple to a clock node.
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