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公开(公告)号：US20220302906A1
公开(公告)日：2022-09-22
申请号：US17838029
申请日：2022-06-10
摘要： Trimming components within an oscillator comprising: a trim-capable current source, wherein the trim-capable current source comprises a trimmable resistor and a trimmable current component, a comparator comprising a first input terminal that couples to the trim-capable current source and the second input terminal that couples to a reference voltage source, a switch coupled to the first input terminal and the trim-capable current source, and a trim-capable capacitor coupled to the switch, wherein the switch is coupled between the trim-capable capacitor and the trim-capable current source.
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公开(公告)号：US11323067B2
公开(公告)日：2022-05-03
申请号：US17235270
申请日：2021-04-20
发明人： Masafumi Nakatani , Hiroki Murakami
IPC分类号： H03B5/04 , G05F3/26 , H03K3/0232 , H03K3/011 , H03K3/0231 , G05F1/573 , H03K5/135 , G05F1/56
摘要： The present invention provides an oscillator circuit and a semiconductor integrated circuit, which can suppress the upper limit of the frequency of a clock signal due to an error of the constant current circuit. The oscillator circuit of the present invention includes a constant current circuit, an oscillator, and a current limiting circuit. The constant current circuit generates a first output current according to a supply voltage. The current limiting circuit receives the first output current and generates a second output current, and establishes an upper limit for the second output current when the supply voltage drops below a lower limit of a guaranteed operational range of the constant current circuit. The oscillator generates a clock signal according to the second output current. By establishing the upper limit for the second output current, the upper limit of the frequency of the clock signal can be suppressed.
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公开(公告)号：US11293891B2
公开(公告)日：2022-04-05
申请号：US16143897
申请日：2018-09-27
IPC分类号： G01N27/327 , G01N33/487 , G01N27/00 , H03K3/03 , G01N27/414 , G01N33/497 , H03K3/0231 , H03M1/60 , B82Y15/00
摘要： Embodiments of the present disclosure relate to various methods and example systems for carrying out analog-to-digital conversion of data acquired by arrays of nanogap sensors. The nanogap sensors described herein may operate as molecular sensors to help identify chemical species through electrical measurements using at least a pair of electrodes separated by a nanogap. In general, the methods and systems proposed herein rely on digitizing the signal as the signal is being integrated, and then integrating the digitized results. With such methods, the higher sample rate used in the digitizer reduces the charge per quantization and, therefore, the size of sampling capacitors used. Consequently, sampling capacitors may be made factors of magnitude smaller, requiring less valuable space on a chip compared to sampling capacitors used in conventional nanogap sensor arrays.
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公开(公告)号：US11101807B2
公开(公告)日：2021-08-24
申请号：US16216162
申请日：2018-12-11
发明人： Erhan Ozalevli , Mustapha El Markhi , Tuli Dake
IPC分类号： H03L7/18 , H03L7/099 , H03L7/085 , H03L7/113 , H03K3/0231
摘要： One example includes a phase-locked loop (PLL) circuit. The circuit includes a frequency divider and phase detector configured to generate a plurality of non-overlapping switching signals based on an input signal and a PLL output signal. The circuit also includes a linear frequency-to-current (F2I) converter configured to generate a control current having an amplitude that is based on the plurality of non-overlapping switching signals. The circuit further includes a linear current-controlled oscillator configured to generate the PLL output signal to have a frequency and phase to be approximately equal to the input signal based on the amplitude of the control current.
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公开(公告)号：US11031940B2
公开(公告)日：2021-06-08
申请号：US16225821
申请日：2018-12-19
发明人： John Paul Lesso
摘要： This application relates to sensing circuits for sensing a physical property or quantity of interest. The sensing circuit has an oscillator comprising a hysteretic comparator and a loop filter configured to output an oscillation signal. The loop filter comprises a first component with an electrical property that varies with the physical property or quantity of interest. A time constant of the loop filter depends on the electrical property of the first component. A decoder is configured to receive the oscillation signal and provide an indication of any change in frequency of the oscillation signal as an indication of a change in the physical property or quantity of interest. The electrical property may be an impedance, such as a resistance.
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公开(公告)号：US11025233B1
公开(公告)日：2021-06-01
申请号：US16841915
申请日：2020-04-07
发明人： Tae Ho Lim
IPC分类号： H03K3/013 , H03K3/011 , H03K4/502 , H03K3/0231
摘要： An oscillator circuit includes a bias circuit, a signal generation circuit, and a control circuit. The bias circuit is configured to generate a reference voltage based on a reference current and a bias resistor. The signal generation circuit is configured to generate a bias current based on the reference current, perform charging and discharging of a capacitor using the bias current, and generate an oscillation signal based on the charging and the discharging of the capacitor. The control circuit is configured to generate a control signal having a constant discharging time, based on the reference voltage and the oscillation signal, controlling the charging and the discharging of the capacitor.
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公开(公告)号：US10754369B2
公开(公告)日：2020-08-25
申请号：US16535372
申请日：2019-08-08
申请人： ROHM CO., LTD.
发明人： Naohiro Nomura , Takatoshi Manabe
IPC分类号： G05F3/26 , H03K3/0231 , G05F3/24 , H03L7/089
摘要： A first transistor and a second transistor have control terminals coupled to each other. A current mirror circuit supplies a current having the same amount as that of a current Iref flowing through a first path including the second transistor to a second path including the first transistor and supplies a current having a predetermined number of times m of a current amount of the current Iref of the first path to a third path separate from the second path. The third transistor and a fourth transistor are provided on the third path. The third transistor has a source coupled to one end of the first transistor, and the fourth transistor has a gate coupled to a gate of the third transistor. A resistor is provided between a source of the fourth transistor and one end of the second transistor.
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公开(公告)号：US10727817B2
公开(公告)日：2020-07-28
申请号：US16597926
申请日：2019-10-10
发明人： Masayuki Kamiyama
IPC分类号： H03K3/00 , H03K3/0231 , G06F1/14 , H03B5/36
摘要： A real-time clock device includes an oscillation circuit configured to generate an oscillation signal using a resonator, a clocking circuit configured to generate present time data based on the oscillation signal, an interface circuit configured to receive a time rewriting request and time rewriting data for the present time data from an external device, and a control circuit configured to perform comparison processing of the present time data of the clocking circuit and the time rewriting data to determine whether the time rewriting data is legitimate.
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公开(公告)号：US10720885B2
公开(公告)日：2020-07-21
申请号：US15668858
申请日：2017-08-04
发明人： Daisuke Kobayashi , Julian Tyrrell
摘要： Relax oscillation circuits have at least one comparison circuit that is structured with a flipped gate transistor and a normal MOS transistor wherein the two transistors having different threshold voltages. The relaxation oscillators are configured for charging and discharging capacitances between the threshold voltages of the flipped gate transistor and the normal MOS transistor by toggling the state of a latching circuit to control the charging and discharging of the capacitances.
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公开(公告)号：US20200228101A1
公开(公告)日：2020-07-16
申请号：US16742030
申请日：2020-01-14
IPC分类号： H03K3/011 , H03K3/012 , H03K3/017 , H03K3/0231
摘要： A device includes a capacitor having a first terminal coupled to a ground node, and a second terminal; a first transistor having a source coupled to the capacitor, a drain coupled to a first node, and a gate; a first current source coupled to the first node and configured to couple to a regulated supply node; a second transistor having a source coupled to the ground node, a drain coupled to a second node, and a gate coupled to the second node and to the gate of the first transistor; and a comparator circuit having an input coupled to the first node and an output configured to couple to a clock node.
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