Invention Grant
- Patent Title: Content aware scheduling in a HEVC decoder operating on a multi-core processor platform
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Application No.: US14723573Application Date: 2015-05-28
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Publication No.: US10827178B2Publication Date: 2020-11-03
- Inventor: AnilKumar Nellore , Padmagowri Pichumani , Vinay Kulkarni , Chetan Kumar Viswanath Gubbi , Shailesh Ramamurthy , Padmassri Chandrashekar
- Applicant: ARRIS Enterprises, Inc.
- Applicant Address: US GA Suwanee
- Assignee: ARRIS Enterprises LLC
- Current Assignee: ARRIS Enterprises LLC
- Current Assignee Address: US GA Suwanee
- Agency: Chernoff, Vilhauer, McClung & Stenzel, LLP
- Main IPC: H04N19/13
- IPC: H04N19/13 ; H04N19/117 ; H04N19/176 ; H04N19/174 ; H04N19/44 ; H04N19/17 ; H04N19/436 ; H04N19/186 ; H04N19/82

Abstract:
A method is provided for decoding an encoded video stream on a processor having a plurality of processing cores includes receiving and examining a video stream to identify any macroscopic constructs present therein that support parallel processing. Decoding of the video stream is divided into a plurality of decoding functions. The plurality of decoding functions is scheduled for decoding the video stream in a dynamic manner based on availability of any macroscopic constructs that have been identified and then based on a number of bytes used to encode each block into which each picture of the video stream is partitioned. Each of the decoding functions is dispatched to the plurality of processing cores in accordance with the scheduling.
Public/Granted literature
- US20150350652A1 CONTENT AWARE SCHEDULING IN A HEVC DECODER OPERATING ON A MULTI-CORE PROCESSOR PLATFORM Public/Granted day:2015-12-03
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