In one embodiment, a processor includes at least one core and at least one graphics processor. The processor includes: a display host controller to control a display device coupled to the processor; a touch host controller to control a touch device coupled to the processor; a traffic controller to multiplex first information from the display host controller and second information from the touch host controller; and a physical unit circuit to communicate the first information and the second information via a plurality of first data lanes of an interconnect to couple to at least one device controller, a clock signal via a clock lane of the interconnect, and receive touch data from the at least one device controller via a second data lane of the interconnect. Other embodiments are described and claimed.