Invention Grant
- Patent Title: Integrated semiconductor processing
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Application No.: US16579756Application Date: 2019-09-23
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Publication No.: US10861722B2Publication Date: 2020-12-08
- Inventor: Benjamin Colombeau , Sheng-Chin Kung , Patricia M. Liu
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: APPLIED MATERIALS, INC.
- Current Assignee: APPLIED MATERIALS, INC.
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson + Sheridan, LLP
- Main IPC: H01L21/67
- IPC: H01L21/67 ; H01L21/3065 ; H01L21/02 ; H01L29/165 ; H01L29/40 ; H01L29/66 ; H01L29/423

Abstract:
Generally, examples described herein relate to integrated solutions for forming cladding layers on trimmed layers that were formed as part of a superlattice. In an example, a first material is selectively etched in a first processing chamber of a processing system. The first material is disposed within alternating layers of the first material and a second material in a channel region on a substrate. A portion of the second material is trimmed in the first processing chamber of the processing system. The substrate is transferred from the first processing chamber of the processing system to a second processing chamber of the processing system without exposing the substrate to an ambient environment exterior to the processing system. A cladding layer is epitaxially grown on respective layers of the trimmed second material in the second processing chamber of the processing system.
Public/Granted literature
- US20200152493A1 INTEGRATED SEMICONDUCTOR PROCESSING Public/Granted day:2020-05-14
Information query
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