Invention Grant
- Patent Title: Techniques to improve linearity of R-2R ladder digital-to-analog converters (DACs)
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Application No.: US16854077Application Date: 2020-04-21
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Publication No.: US10862493B2Publication Date: 2020-12-08
- Inventor: Atul Kumar Agrawal , Gautam Salil Nandi , Siddharth Malhotra , Tanmay Neema
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent John R. Pessetto; Charles A. Brill; Frank D. Cimino
- Main IPC: H03M1/10
- IPC: H03M1/10 ; H03M1/12 ; H03M13/11

Abstract:
An integrated circuit includes a digital-to-analog converter (DAC) core including a plurality of thermometric arms and an R-2R ladder, the DAC core to convert a DAC code to an analog signal. The integrated circuit includes additional components as well. A differential non-linearity (DNL) calibration circuit outputs DNL coefficients based on the DAC code. A memory stores a value indicative of a product of a resistor temperature coefficient (TC) and a resistor self-heating coefficient (SHC). A current DAC (IDAC) couples to the R-2R ladder. A self-heating calibration circuit generates a self-heating trim code based on the value from the memory. An adder adds a value indicative of the DNL coefficients with the self-heating trim code to generate an IDAC trim code and provides the IDAC trim code to the IDAC to trim the R-2R ladder.
Public/Granted literature
- US20200252073A1 TECHNIQUES TO IMPROVE LINEARITY OF R-2R LADDER DIGITAL-TO-ANALOG CONVERTERS (DACs) Public/Granted day:2020-08-06
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