Invention Grant
- Patent Title: Compact antifuse element and fabrication process
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Application No.: US16525780Application Date: 2019-07-30
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Publication No.: US10886283B2Publication Date: 2021-01-05
- Inventor: Abderrezak Marzaki , Pascal Fornara
- Applicant: STMicroelectronics (Rousset) SAS
- Applicant Address: FR Rousset
- Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee Address: FR Rousset
- Agency: Crowe & Dunlevy
- Priority: FR1857122 20180731
- Main IPC: H01L27/11
- IPC: H01L27/11 ; H01L27/112 ; H01L23/00 ; G11C17/18 ; G11C17/16 ; H01L23/525

Abstract:
An integrated circuit includes at least one antifuse element. The antifuse element is formed from a semiconductor substrate, a trench extending down from a first face of the semiconductor substrate into the semiconductor substrate, a first conductive layer housed in the trench and extending down from the first face of the semiconductor substrate into the semiconductor substrate, a dielectric layer on the first face of the semiconductor substrate, and a second conductive layer on the dielectric layer. A program transistor selectively electrically couples the second conductive layer to a program voltage in response to a program signal. A program/read transistor selectively electrically couples the first conductive layer to a ground voltage in response to the program signal and in response to a read signal. A read transistor selectively electrically couples the second conductive layer to a read amplifier in response to the read signal.
Public/Granted literature
- US20200043936A1 COMPACT ANTIFUSE ELEMENT AND FABRICATION PROCESS Public/Granted day:2020-02-06
Information query
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