A resistive memory device may include a plurality of MATs, row control blocks, a plurality of word lines, a plurality of bit lines and memory cells. Each of the row control blocks may be interposed between the MATs. Each of the row control blocks may include a control element. The word lines may be arranged spaced apart from each other by a substantially uniform gap on the MATs. The bit lines may overlap with the word lines. The memory cells may be located between the word lines and the bit lines. Each of the word lines may be electrically connected with the control element of each of the row control blocks via a connection path.