Memories, and systems incorporating similar memories, as well as their operation, where the memory might include an array of memory cells, a status register, and a controller configured to access the array of memory cells. The controller may further be configured to perform a plurality of read operations on the array of memory cells in response to a read command associated with a plurality of addresses, store a particular value to the status register in response to data of a particular read operation corresponding to a particular address of the plurality of addresses being available for readout by an external device, and store a different value to the status register in response to data of a different read operation corresponding to a different address of the plurality of addresses being available for readout by the external device.