Systems, methods, and apparatuses relating to performing stencil configuration and computation operations are described. In one embodiment, a matrix operations accelerator circuit includes a two-dimensional grid of fused multiply accumulate circuits coupled by a network; a first plurality of registers that represents a first two-dimensional matrix coupled to the matrix operations accelerator circuit; a second plurality of registers that represents a second two-dimensional matrix coupled to the matrix operations accelerator circuit; a decoder, of a core coupled to the matrix operations accelerator circuit, to decode a single instruction into a decoded single instruction; and an execution circuit of the core to execute the decoded single instruction to: switch the matrix operations accelerator circuit from a first mode to a second mode where a first set of input values from the first plurality of registers is sent to a first plurality of fused multiply accumulate circuits that form a first row of the two-dimensional grid, a second set of input values from the first plurality of registers is sent to a second plurality of fused multiply accumulate circuits that form a second row of the two-dimensional grid, a first coefficient value from the second plurality of registers is broadcast to a third plurality of fused multiply accumulate circuits that form a first column of the two-dimensional grid, and a second coefficient value from the second plurality of registers is broadcast to a fourth plurality of fused multiply accumulate circuits that form a second column of the two-dimensional grid.