Invention Grant
- Patent Title: DSP execution slice array to provide operands to multiple logic units
-
Application No.: US15726305Application Date: 2017-10-05
-
Publication No.: US10922098B2Publication Date: 2021-02-16
- Inventor: Gregory Edvenson , Jeremy Chritz , David Hulton
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: MICRON TECHNOLOGY, INC.
- Current Assignee: MICRON TECHNOLOGY, INC.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F15/80 ; G06F9/448 ; G06F8/30 ; G06F9/445

Abstract:
Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include a first configurable logic unit configured to receive a first operand and a second operand; a second configurable logic unit configured to receive a third operand and the first calculated operand; a first switch configured to receive the first operand and a fourth operand and to output a first selected operand; and a second switch configured to receive the second calculated operand and the first selected operand.
Public/Granted literature
- US20190108040A1 CONFIGURABLE DIGITAL SIGNAL PROCESSOR FRACTURING AND MACHINE LEARNING UTILIZING THE SAME Public/Granted day:2019-04-11
Information query